A Tour of a PCIe 3.0 Test Setup

Figure 1: Test-equipment requirements for PCIe 3.0

Having examined the complex machinations of PCIe 3.0 dynamic link equalization in earlier posts (see the links below), now we will look at a typical test setup for design and debug and/or compliance testing. Then we will move on to some test examples showing some common problems that one might encounter.

What Is An Optical Modulation Analyzer?

Figure 1: A representative block diagram of a coherent
transmitter and receiver

In an earlier post, we looked at some of the fundamentals of coherent signals: what comprises a coherent signal, how and why they're used, and a bit about how they're represented visually on an oscilloscope. The advent of coherent signals has brought about the rise of a new class of test instrumentation, known as an optical modulation analyzer (OMA). In this post, we'll examine what an OMA is and what it brings to the party above and beyond a stand-alone oscilloscope.

Test Challenges for PAM4 Signals

The major test challenges posed by PAM4 signals

PAM4 encoding offers the advantage of doubling the bit rate in a serial data channel, doing so by increasing the number of voltage levels from two to four. It's a fairly complex modulation scheme, so it should be no surprise that it presents some test and measurement challenges.

The History of Jitter (Part II)

Figure 1: An example of using histograms to plot
the statistical distribution of edge arrival times

Resuming our review of the history of jitter and the evolving response to it, we'd arrived at the late 1990s, when more sophisticated analysis methods were necessary to get a good handle on jitter. In particular, statistical analysis came onto the scene. Statistics are a great tool for analyzing phenomena such as jitter that change more as you look at them harder.

The History of Jitter

Figure 1: The story of jitter spans 45-baud telegraph
machines to 160-Gbaud optical fiber

Jitter is a signal-integrity gremlin that's been with us for a long time. In fact, it's been with us since before anyone really needed to care about it. But as time has worn on, our perception of jitter has certainly changed, and with it our approaches to diagnosing it, measuring it, and ultimately dispatching it. Here, we'll begin a traversal of the "jitter story," surveying where we've been, where we are, and where we may be going in our dealings with the phenomenon.

Plan For Successful USB Compliance Testing (Part II)

Figure 1: A representative transmitter
compliance test setup

In the first post in this series, we looked at some of the basics of USB 3.0 and 3.1 compliance test and covered the USB-IF's role in overseeing the protocol. Now, let's look into some aspects of physical-layer test.

PCIe 3.0 Dynamic Link EQ: De-Emphasis, Preshoot, Cursors, and Presets

Figure 1: De-emphasis, a key transmit-side equalization
technique for PCIe 3.0, boosts high-frequency content

In an earlier post, we looked at some of the basics of dynamic link equalization for PCIe 3.0, and in particular the reasons why it's not only necessary but mandated by the PCI-SIG for compliance testing. Essentially, the boost in data rates from 5 GT/s in PCIe 2.0 to 8 GT/s in PCIe 3.0 wreaked havoc in terms of signal integrity in the channel. The solution is found in equalization both before (TxEQ) and after (RxEQ) the channel.

The Hows and Whys of PCIe 3.0 Dynamic Link Equalization

Figure 1: SI problems are the root cause for
dynamic link equalization in PCIe 3.0

If you're designing a computer peripheral these days, chances are that you'll use the Peripheral Component Interconnect Express (PCIe) protocol for communication between the device and the host system. With the emergence of PCIe, a bunch of older bus standards were kicked to the curb. PCIe itself became the basis for more specialized standards, most notably ExpressCard for laptop expansion cards and SATA Express for storage interfaces.

Measuring Time-Interval Error in Serial Data Waveforms

Figure 1: The first step in quantifying jitter is to
determine measured times of arrival for bit transitions

A recent post covered some of the reasons why one might want to measure jitter. In design and debug of serial-data channels, jitter is among the most prevalent causes of unacceptable bit-error rates (BERs). In that earlier post, we looked at the physical phenomenon of jitter and why it wreaks the havoc that it does. In the present installment, we will look in broad terms at how jitter is measured and quantified.

Why Should You Measure Jitter?

Figure 1: Designing a serial-data channel with first-pass
success means analysis and mitigation of jitter sources

As mentioned in an earlier post on some basics of jitter, the bane of serial-link design is a signal that doesn't arrive at its destination when it should, whether early or late. The goal of serial-link design and implementation is to transmit data with as few bit errors as possible. Thus, analyzing jitter is a key element of achieving first-pass design success.