Introduction to Debugging High-Speed Serial Links

Figure 1: These images depict the degradation of serial data
traffic as it makes its way from transmitter to receiver

In recent years, the data rates in serial links have increased exponentially across any number of standard protocols, including PCI Express, USB, and even SATA and SAS. With higher data rates comes more challenges for system designers, validation engineers, and test engineers with respect to signal integrity (SI). Some SI effects are much more prominent at higher data rates than they were for lower-speed versions of the same protocols. In this series of posts, we'll examine these SI effects, look at some methods of improving system performance, and discuss some SI analysis solutions as well as measurement considerations.

Measuring Time-Interval Error in Serial Data Waveforms

Figure 1: The first step in quantifying jitter is to
determine measured times of arrival for bit transitions

A recent post covered some of the reasons why one might want to measure jitter. In design and debug of serial-data channels, jitter is among the most prevalent causes of unacceptable bit-error rates (BERs). In that earlier post, we looked at the physical phenomenon of jitter and why it wreaks the havoc that it does. In the present installment, we will look in broad terms at how jitter is measured and quantified.