Oscilloscope Basics: Multiplexed Front Panel Controls

Fig. 1. Modern,
slim front panel.

Most Teledyne LeCroy oscilloscopes are equipped with traditional front panel controls—knobs and buttons—that are a (literally) handy way to make basic acquisition settings such as gain, timebase and trigger level. While all these could be made using the oscilloscope software, using the front panel allows you to keep dialogs closed and more of the screen “real estate” available for viewing traces as you modify these settings.

In order to optimize that real estate, front panels have become increasingly slim, and many front panel controls on newer Teledyne  LeCroy oscilloscopes are multiplexed, meaning they have multiple functions or can be used to control multiple on-screen objects. Here is a list of tips to keep in mind when using the front panel.

Fundamentals of Power Integrity: Mutual Aggressors and Rail Transient Response Measurement

Fig 1. Rail droop in response to a load step is
a typical case of mutual aggressors in a PDN.

A third type of noise found in PDNs is what we call mutual aggressors, which is crosstalk coupling from one component of the PDN onto another.

An obvious example is a load step in the PDA, where something in the system being turned on pulls current from the VRM that supplies a rail. In Figure 1, you can see how the output voltage of the VRM supplying a 1 V rail droops in response to a load step before it recovers. This is still noise: it is a signal variation that we're not expecting and don't want.

We want to be able to characterize that noise, because too much droop could affect the operation of other components that are already consuming power from that device.

In order to do so, we’re going to measure the rail transient response to the load application. We need only look at two signals: the voltage and the current on the rail of interest. Figure 1 shows the voltage on C5 (the green trace) and the current on C8 (the orange trace).

Your Ground Bounce Questions Answered

Figure 1. Line set to "quiet low" shows ground
bounce occurring as I/O driver switches.

During an October 2020 webinar, Don’t Let Ground Bounce RuinYour Day, Dr. Eric Bogatin was asked several questions regarding his topic of presentation. Here are his answers.

Q: From what frequency should we consider ground bounce to be a problem?

A: Ground bounce is really due to a dI/dt. Generally, it becomes a problem with rise times shorter than 100 ns. The bandwidth of this is about 3.5 MHz. This means ground bounce can be an issue at relatively low frequency.

Which Virtual Probing Method to Use?

 

Virtual probing lets you "probe" where a probe
can't reach, or compensate signals by deembedding
or simulating devices and channels.

A great feature of Teledyne LeCroy oscilloscopes is the ability to apply virtual probing to compensate an input signal, whether by deembedding fixtures from the signal path, or simulating a “missing” component. It is especially helpful in cases where the signal is difficult to probe at the ideal location, hence the concept of “virtual” probing.

For example, because the JEDEC electrical specifications are defined at the balls of the DDR DRAM, it is often necessary to use the virtual probing capabilities of the oscilloscope to get the best representations of DDR signals to be analyzed with DDR Debug Toolkit or QualiPHY compliance software.

Here, we’ll give an overview of the virtual probing methods that become available with the installation of the SDAIII-CompleteLinQ or VirtualProbe software options, and some guidance as to which method is best to use in which case. And although we’ll show examples drawn from DDR analysis, the benefits of virtual probing are by no means limited to DDR signals.

Fundamentals of Power Integrity: Board Pollution

Figure 1. "Pollution" occurring on PDN traces.

Board pollution is noise occurring on the packages and interconnects (traces and planes) that carry current from the VRMs to the consumer devices.
One place it can originate is from the VRM itself, for example, with the switching noise the VRM generates (Figure 1). That can be a real concern if the board capacitance means you have a resonance around the switching frequency that would act as an amplifier for the switching noise and cause all kinds of problems with other devices on the board.

Fundamentals of Power Integrity: Self-aggression Noise

Fig. 1: VRM-switching noise is a self aggressor that can be
identified because it is synchronous with the PWM clock. 

Self-aggression noise is so-called because it is inflicted by a component onto itself through its normal operation; nothing else in the system is affecting it. When we look for this, we want to ensure the system is in a steady state, in a place where the noise environment is fairly clear (e.g., the device is on an evaluation board).

An example of self-aggression would be VRM-switching noise. Figure 1 shows ripple on a 900 millivolt rail (yellow trace) at a time when no load is present. One of the things that tells us this is switching noise is that it is synchronous to the PWM clock (red trace). Ripple that is synchronous with the switching clock is a typical figure of merit for identifying switching noise.

Fundamentals of Power Integrity: Characterizing PDN Noise

Figure 1. Noise tolerances for embedded system
components are becoming ever tighter.

Power integrity concerns maintaining the quality of power from generation to consumption in an embedded system. “Good” power integrity could be defined as having noise levels that are within tolerance. This short series will focus on characterizing noise on your power delivery network (PDN), with the goal of knowing where you must adjust your design to meet those tolerances.

Why do we care about voltage rail noise? As electronic designs strive for ever lower power consumption, power rails already carry very low voltages, often 1 V or less. Components like RF receivers, ADCs and DACs can be affected by noise of less than 1% of the rail value (Figure 1). This means noise tolerances can be as tight as single-digit millivolts, which is why power integrity takes up considerable validation time in labs.