Isolated Oscilloscope Inputs vs. Isolated Oscilloscope Probes

Some users in high-voltage test environments seek measuring instruments with isolated inputs because they want the safety and convenience of isolation without having to spend money on an isolated oscilloscope probe, like the Teledyne LeCroy DL-ISO or the Tektronix IsoVu®. While that's understandable, isolated inputs built into the instrument channel may be convenient, but they don't necessarily give you good performance, certainly not as good as  you would get from a high quality, high-voltage isolated probe.

Figure 1. Cascaded H-bridge signals captured using an isolated input (left) and an isolated probe (right).

Choosing a High-voltage Oscilloscope Probe for SiC/GaN Power Semiconductor Device Measurements

Figure 1: Wide-bandgap (GaN) power semiconductor device
waveforms captured using two, different probe topologies.
Click on any image to expand.

In our last post, we introduced you to a new tool on the Teledyne LeCroy website: The High-voltage Probe Selection Guide. To demonstrate the benefits of the guide, let’s explore further what must be considered when choosing an HV oscilloscope probe for power semiconductor device measurements.

Why are power semiconductor device measurements challenging?

How to Choose the Best High-voltage Oscilloscope Probe in 5 Minutes

Figure 1: The High-voltage Probe Selection Guide
color codes better or worse probe selections based on
your answers to three, simple questions.
Click any image to enlarge.

Probing high-voltage (HV) circuits for analysis with an oscilloscope presents unique challenges due to the potential for injury or equipment damage, as well as the demands of the materials used in HV semiconductors. HV floating measurements are extremely dangerous and difficult to make. Conventional passive probes are not the answer, but isolated and high-voltage differential probes are options. Yet, with many possible choices in these categories, how can you decide which is actually the best HV oscilloscope probe for your application?

Teledyne LeCroy offers this new, easy way to help you select a high-voltage oscilloscope probe based on your specific application—the High-voltage Probe Selection Guide—available on the Teledyne LeCroy website at: teledynelecroy.com/powerprobes

Physical-Layer Collision Avoidance in 10Base-T1S Automotive Ethernet

Fig.1, 10Base-T1S PLCA cycle. If there is no data
traffic (top), only BEACONs are seen on the bus. 
Data from a node (bottom) will expand the time
between two BEACONs.

10Base-T1S (IEEE 802.cg) is a variant of Automotive Ethernet  that supports half-duplex and full-duplex communication, allowing either a point-to-point direct connection between two nodes, or use of a multidrop topology with up-to-eight nodes connected on a single 25 m bus segment.

Multidrop cabling of one bus line provides options to extend and scale with fewer physical wires and less weight than point-to-point topologies. With minimum connector space at the ECU, the bus line can be expanded simply by adding sensor units. A bus line with additional sensor units for ultrasonic and short-range radar is an example of how multidrop cabling can be scaled.  

Among the main objectives of the 10Base-T1S PHY layer are reconciliation of transmissions from a variety of mediums, ensuring cooperative behavior by the nodes on a multidrop bus. One way it does this is through the use of Physical-Layer Collision Avoidance (PLCA) technology to minimize dead time and avoid collisions. In this post, we'll describe the workings of PLCA and in a future post, how you can debug PLCA timing issues using an oscilloscope with the 10Base-T1S TDME software.

10Base-T1S Automotive Ethernet vs. 10Base-T1L Industrial Ethernet

Figure 1: 10Base-T1S and 10Base-T1L differ primarily in
reach, encoding methods, topology and applications.

10Base-T1S, a variant of Automotive Ethernet, and 10Base-T1L, also known as Industrial Ethernet, are Single Pair Ethernet (SPE) protocols described in IEEE 802.cg standards. Both offer the same 10 Mb/s communication speed using a single, unshielded twisted pair (T1), but differ in specifics of reach, encoding schemes and topologies, as well as their principal applications.

Using TF-USB-C-HS for USB 3.2 PHY-Logic Layer Debug

Figure 1. USB 3.2 electrical decoding with ProtoSync
view of protocol packets, captured using TF-USB-C-HS.
Click on any image to enlarge it.

In a USB-C connector, link training for USB 3.1/3.2 is negotiated using an LTSSM (Link Training and Status State Machine) through electrical signaling on the TX1/RX1 and TX2/RX2 connector pins. Link training must be completed on the link before high-speed data transactions can occur.  One problem you might encounter during link training is a failure to train to USB 3.2 Gen 2 specifications. Teledyne LeCroy customers report that most system-interoperability problems are caused by either link-training or sideband-negotiation failures, which in turn can result from an electrical problem, a digital problem or a combination of both. 

TF-USB-C-HS enables you to probe all points on the USB-C connector to measure and analyze live links. The insertion-loss profile of the included cable and coupon is tuned to be the equivalent of a golden 0.8-m USB Type-C cable, so you can replace a 0.8-m cable with the coupon and not experience any difference in link performance. The coupon also has a loop to allow a current probe to make load-current measurements, and the HS version is compatible with Teledyne LeCroy DH Series probes for making high-speed differential measurements.

We'll show how to trigger, acquire and decode to find problematic link training packets synchronous with the physical-layer electrical waveforms, so you can tell if the source of your interoperability  problem is electrical, logical or both.

Signal and Power Integrity Tutorial: Power Rail Probing for Rail Compression

Figure 3. Equivalent circuit of a typical CMOS I/O
showing the connection from the on-die rails
and the board-level test points.

By Prof. Eric Bogatin,
Teledyne LeCroy Fellow

Excerpted by permission from the Signal Integrity Journal article, Measuring Only Board-level Power Rail Noise May Be Misleading

Continued from Part 1.

Measuring Rail Compression on the Die

In most applications, we do not have access to the bare die when the chip is assembled on the circuit board. If the IC package has not been instrumented with special pass-through features connecting the rails on the die to board pins, we have to rely on a special trick. [The use of a quiet HIGH and quiet LOW]

When the I/Os of a chip all share the same power and ground rails, which is often the case in small microcontroller devices, designated I/Os can be used as sense lines to measure externally the power rails on the die.