Four Measurement Best Practices

To start the New Year right, we’re going to talk about four measurement "best practices", which will help you get the most out of any oscilloscope you have. These are important when doing any type of measurement—and you can get a good start on them simply by asking yourself the four questions in the sidebar.

1. Anticipate the results

Those who are familiar with Dr. Eric Bogatin’s Rule #9 will know this one. Before you do any measurement, anticipate what you expect the result to be, because that is the most important way of identifying if there is a potential problem. 

Decision Feedback Equalization in DDR

Figure 1. A transmitted rectangular pulse suffers
distortion by the time it reaches the receiver. 
Broadening and reflections from previous
transmitted bits add to the pulse response, 
creating inter-symbol interference.

High-speed serial links such as those used in DDR4 and DDR5 are subject to a variety of signal degradation challenges.  Insertion losses, frequency dependent attenuation and inter-symbol interference (ISI), as well as others, are among the most commonly encountered sources of signal degradation. 

Figure 1 shows how reflections can cause ISI on a rectangular pulse. When a rectangular pulse is transmitted, it suffers distortion which is apparent when it reaches the receiver.  It may be broadened due to group delay dispersion because different frequency components of the signal propagate along the signal path at differing velocities. In addition, there may be echo pulses, due to impedance mismatches in the channel.  These mismatches cause reflections that propagate back and forth over the channel and appear as these echoes where subsequent bits should be.

Generally, these signal losses can be compensated for using any of several equalization techniques. The commonly used equalization techniques are feed forward Equalization (FFE), Continuous Time Linear Equalizations (CTLE), and Decision Feedback Equalization (DFE).  FFE and CTLE basically filter the signal to increase the amplitude of high frequency signal components eliminating the frequency dependent attenuation of the signal path. 

Figure 2. Example of a 4-tap DFE equalizer.

DFE is a non-linear equalizer which quantizes the signals and feeds back discrete symbols, as shown in Figure 2.

The DQ signal goes through an analog gain adjustment stage and is applied to a summer.  The output of the summer goes to the first slicer, implemented as a flip flop, where the logical state (0 or 1) is determined, and the signal is delayed by one clock cycle.  The signal propagates through a total of four such slicers.  The output of each slicer is weighted by individual tap weights T1 – T4 and is then fed back to the summer where the weighted sum is subtracted from the DQ signal.  The feedback returns the scaled copies of the last four bits to the input.  This effectively removes ISI from the input. Since the signal is quantized and noise component is ignored in that process it is not propagated.  The clock is required to assure correct timing of the summation components.

DDR5 specifies the use of Decision Feedback Equalization or DFE.  DFE is used rather than FFE or CTLE because it provides equalization without increasing the noise level on the signal. FFE and CTLE basically boost the high frequency response of the channel to compensate for the channel’s frequency dependent attenuation.  The boost is the result of an analog filtering process. This has the effect of increasing noise and noise-like effects like crosstalk, as well.  The slicer stages in DFE quantizes the signal ignoring the noise voltage, and it does not propagate noise to the output of the equalizer. So, it provides high frequency boost without the noise.

In addition to the excellent noise performance, DFE is relatively inexpensive to implement.

The DFE equalizer has one possible negative characteristic: if one of the slicers makes an incorrect determination, then the output will see a burst of errors until the sequence is cleared.  This is a not common event, especially if the data sequence is random.

The DDR Debug Toolkit includes tools for setting up DFE. The weight of each tap can be entered manually, or the DFE can be “trained”.  The training process will automatically determine and enter the correct tap weights.

To learn more about DDR testing and our DDR solutions, watch the on-demand webinar, DDR4/5 & LPDDR4/5 Probing and Debug Solutions.

Also see:

Which Virtual Probing Method to Use?

Isolating DDR Read and Write Operations

Removing Reflections from DDR Signals Probed Mid-Bus

Removing Reflections from DDR Signals Probed Mid-Bus

Figure 1. Virtual probing methods like VP@Rcvr can help
remove reflections from signals probed mid-bus.

Probing DDR signals can present some interesting challenges. The JEDEC specification indicates that all measurements should be made at the output pins of the memory chip. The challenge comes because sometimes the pins of the memory chip are not accessible. You may be able to use an interposer, but even that requires some spatial displacement from the probing point to the Ball Grid Array (BGA) pins of the memory chip. 

If the board has already been populated, there is an even greater problem because the interposer can’t be used, so probes may have to be placed in the middle of the bus in order to make a measurement. In this situation, the probe picks up signals reflected from the memory controller and the memory chip, as well as the desired signals. Reflections appear as non-monotonic ripples on the edges of DQ and DQS signals, as shown in Figure 2.

Isolating DDR Read and Write Operations

Figure 1. DDR DQ and DQS signals are
in phase during a Read operation and
out of phase during a Write operation.

Whether you are debugging or running compliance tests on Double Data Rate (DDR) or Low Power Double Data Rate (LPDDR) memory, the analysis process requires the separation of Read and Write operations to enable measurements on each distinct operational mode. 

The phase relationship between the Data (DQ) signal and the Data Strobe (DQS) signal indicates the type of operation, as shown in Figure 1.

The DQ and DQS signals are phase aligned with edges overlapping in Read mode. In Write mode, they are out of phase, and the DQS edge overlaps the center of the DQ eye.  In the lower speed versions of DDR memory devices, the measuring instrument could be triggered on this phase difference, enabling the isolation of the desired operation for testing.

Oscilloscope Basics: Multiplexed Front Panel Controls

Fig. 1. Modern,
slim front panel.

Most Teledyne LeCroy oscilloscopes are equipped with traditional front panel controls—knobs and buttons—that are a (literally) handy way to make basic acquisition settings such as gain, timebase and trigger level. While all these could be made using the oscilloscope software, using the front panel allows you to keep dialogs closed and more of the screen “real estate” available for viewing traces as you modify these settings.

In order to optimize that real estate, front panels have become increasingly slim, and many front panel controls on newer Teledyne  LeCroy oscilloscopes are multiplexed, meaning they have multiple functions or can be used to control multiple on-screen objects. Here is a list of tips to keep in mind when using the front panel.

Fundamentals of Power Integrity: Mutual Aggressors and Rail Transient Response Measurement

Fig 1. Rail droop in response to a load step is
a typical case of mutual aggressors in a PDN.

A third type of noise found in PDNs is what we call mutual aggressors, which is crosstalk coupling from one component of the PDN onto another.

An obvious example is a load step in the PDA, where something in the system being turned on pulls current from the VRM that supplies a rail. In Figure 1, you can see how the output voltage of the VRM supplying a 1 V rail droops in response to a load step before it recovers. This is still noise: it is a signal variation that we're not expecting and don't want.

We want to be able to characterize that noise, because too much droop could affect the operation of other components that are already consuming power from that device.

In order to do so, we’re going to measure the rail transient response to the load application. We need only look at two signals: the voltage and the current on the rail of interest. Figure 1 shows the voltage on C5 (the green trace) and the current on C8 (the orange trace).

Your Ground Bounce Questions Answered

Figure 1. Line set to "quiet low" shows ground
bounce occurring as I/O driver switches.

During an October 2020 webinar, Don’t Let Ground Bounce RuinYour Day, Dr. Eric Bogatin was asked several questions regarding his topic of presentation. Here are his answers.

Q: From what frequency should we consider ground bounce to be a problem?

A: Ground bounce is really due to a dI/dt. Generally, it becomes a problem with rise times shorter than 100 ns. The bandwidth of this is about 3.5 MHz. This means ground bounce can be an issue at relatively low frequency.