|Figure 1: Designing a serial-data channel with first-pass|
success means analysis and mitigation of jitter sources
The physical makeup of a typical serial-data channel (Figure 1) is chock-full of structures that are potential sources of jitter. Impedance mismatches can crop up anywhere in the critical path, which includes elements such as microstrip lines, vias, connectors, decoupling capacitors, and board/chip interfaces.
|Figure 2: Two examples of bit errors|
It's impossible to design a high-speed serial-data channel that is completely free of bit errors. But what the design team should be chasing is the lowest possible bit-error rate (BER). The specifications for most serial-data protocol standards demand a very low BER. For example, the specification for USB 3.1 calls for a BER of less than one in every 10-12 bits at data rates of 5 GT/s. Failing to meet that requirement can prove quite costly.
|Figure 3: A graphic illustration|
While a low BER is the overall goal for the data channel's design, the quantification of the jitter that causes bit errors is arrived at through measurement and subsequent analysis of time-interval errors (TIE).
Hopefully, this post fills in the reason why one would measure jitter (quantified in TIE) in the first place. Measuring time-interval errors is a multi-step process, and in subsequent posts in this series on jitter, we'll cover that process as well as the subsequent analysis of the measurement results.