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Showing posts with label continuous time linear equalization. Show all posts
Showing posts with label continuous time linear equalization. Show all posts

23 July 2018

Feed-Forward Equalization

FFE creates a number of delayed versions of the input signal that are then added back to the signal with proper weights
Figure 1: FFE creates a number of delayed versions of the
input signal that are then added back to the signal with
proper weights
In addition to continuous time linear equalization (CTLE), another means of improving signal quality at the receiver end of a high-speed serial data link is known as feed-forward equalization (FFE). In terms of implementation, FFE is not unlike the pre-emphasis filtering that is done on the transmitter side. An FFE implementation looks for all intents and purposes like a digital finite impulse response (FIR) filter.

17 July 2018

Continuous Time Linear Equalization

A CTLE implementation at the receiver end of a serial-data channel seeks to boost higher frequencies while not boosting noise any more than necessary
Figure 1: A CTLE implementation at the receiver end of a
serial-data channel seeks to boost higher frequencies while
not boosting noise any more than necessary
We've been looking at the broad topic of debugging high-speed serial links, and in that context, we're also touching on ways to improve signal performance on the receiver side. One of those ways is to implement continuous time linear equalization (CTLE).

10 November 2014

PCIe 3.0 Dynamic Link EQ: De-Emphasis, Preshoot, Cursors, and Presets

De-emphasis, a key transmit-side equalization technique for PCIe 3.0, boosts high-frequency content
Figure 1: De-emphasis, a key transmit-side equalization
technique for PCIe 3.0, boosts high-frequency content
In an earlier post, we looked at some of the basics of dynamic link equalization for PCIe 3.0, and in particular the reasons why it's not only necessary but mandated by the PCI-SIG for compliance testing. Essentially, the boost in data rates from 5 GT/s in PCIe 2.0 to 8 GT/s in PCIe 3.0 wreaked havoc in terms of signal integrity in the channel. The solution is found in equalization both before (TxEQ) and after (RxEQ) the channel.

06 November 2014

The Hows and Whys of PCIe 3.0 Dynamic Link Equalization

SI problems are the root cause for dynamic link equalization in PCIe 3.0
Figure 1: SI problems are the root cause for
dynamic link equalization in PCIe 3.0
If you're designing a computer peripheral these days, chances are that you'll use the Peripheral Component Interconnect Express (PCIe) protocol for communication between the device and the host system. With the emergence of PCIe, a bunch of older bus standards were kicked to the curb. PCIe itself became the basis for more specialized standards, most notably ExpressCard for laptop expansion cards and SATA Express for storage interfaces.