Get Ready for PCIe 6.0 Base Tx Testing--Compliance, Jitter and Eye Diagrams

Figure 1. The four levels and three eyes of the
PCIe 6.0 PAM4 signal.
Click on any image to enlarge.

The PCI Express® 6.0 Base specification was officially released in January 2022 at version 1.0, meaning it is considered final. The CEM and PHY test specifications are currently at version 0.3, and 0.5 versions of both will probably be released sometime in the third or fourth quarter of 2022. As both the CEM and PHY test specifications are still at an early stage, it's hard to predict exactly when the PCIe® 6.0 compliance test program will start, but it's safe to say it is at least a few years out. However, PCIe 6.0 Base testing is upon us, especially those of us working on chip design.

So, what can implementers expect as they retool for PCIe 6.0 Base Tx and Base Rx physical layer testing?

Test Challenges for PAM4 Signals

The major test challenges posed by PAM4 signals

PAM4 encoding offers the advantage of doubling the bit rate in a serial data channel, doing so by increasing the number of voltage levels from two to four. It's a fairly complex modulation scheme, so it should be no surprise that it presents some test and measurement challenges.

PAM4 Test Setups Vary With Applications

Figure 1: A high-level view of PAM4 use cases

In an earlier post, we surveyed the basic properties of PAM4 signals. Now, we will examine some of the ways in which PAM4 is finding application in the real world and what test and measurement setups might look like for those applications.