PCI Express 4.0 Error Detection Using a BERT and Oscilloscope

Figure 1: BERT and Oscilloscope connection
for PCI Express 4.0 error detection.

The PCI Express® 4.0 standard specification requires an oscilloscope with at least 25 GHz analog bandwidth and a BERT which can test bit rates of at least 16 Gbps. The BERT provides a known input pattern to the PCIe® device under test (DUT), and the DUT is instructed to regenerate the identical bit pattern while placed in loopback mode. Since a BERT can output a signal when a bit error is detected, this signal can be input to the oscilloscope to trigger a synchronized capture when an error occurs. By combining the capabilities of these two instruments, a powerful combination of real-time error detection and characterization can emerge.

Connecting the Instruments

In Figure 1, a known pattern is connected from the BERT PPG D1 output to the PCIe DUT input via a 2.92 mm K-type cable. The DUT attempts to regenerate the same data pattern, while the DUT output is routed to both the BERT error detector input and the oscilloscope channel 1 via 2.92 mm K-type tables and a power splitter. An error-free reference signal is connected between the BERT D2 output to the oscilloscope channel 2, along with the error trigger signal from the error detector output to the oscilloscope channel 3. An oscilloscope Edge trigger is set on the rising edge of the error detector output signal on C3.

A Tour of a PCIe 3.0 Test Setup

Figure 1: Test-equipment requirements for PCIe 3.0

Having examined the complex machinations of PCIe 3.0 dynamic link equalization in earlier posts (see the links below), now we will look at a typical test setup for design and debug and/or compliance testing. Then we will move on to some test examples showing some common problems that one might encounter.

PCIe 4.0 PLL Bandwidth Testing

Figure 1: PLL bandwidth testing
ensures that the add-in card's
PLL bandwidth and peaking
are within specifications

The final piece of the PCIe 4.0 compliance-test puzzle—at least until PCI-SIG completes its test definitions—is the PLL bandwidth test. This test, which is performed only on add-in cards, verifies that the PLL bandwidth and peaking are within the limits allowed by the PCIe 4.0 specification (Figure 1).

PCIe 4.0 Receiver Link-Equalization Testing (Part II)

Figure 1: Working out the optimal combination of Tx emphasis
presets and receiver CTLE settings

As may be apparent from our previous post on PCIe 4.0 receiver link-equalization testing, this part of the PCIe 4.0 compliance tests is somewhat involved. When we left off last time, we were in the midst of receiver calibration, looking to ensure that the test-signal eye is as closed as possible without violating the specification limits.

PCIe 4.0 Receiver Link-Equalization Testing (Part I)

Figure 1: PCIe 4.0 receiver link-equalization testing
takes place at the site of the channel's worst-case signal

In the battery of PCIe 4.0 compliance tests, there is but a single test of receiver behavior: Rx link-equalization testing. Given that our DUT in this test is an add-in card, we want to have our worst-case signal at the Card ElectroMechanical (CEM) connector (Figure 1). The signal then proceeds through the channel on the add-in card to the end point, which is the receiver on the DUT.

PCIe 4.0 Transmitter Link-Equalization Testing

Figure 1: Shown is an overview of the PCIe 4.0
link-equalization response test

PCI Express has seen steady, and significant, increases in bit rates in each generational revision. Most recently, bit rates leaped from 8 Gb/s in PCIe 3.0 to 16 Gb/s in the current version 4.0. With these speed increases has come the need for dynamic link equalization, which becomes necessary for the sake of signal integrity. Compliance tests for dynamic link equalization is where things start to get a little more sophisticated, particularly when it comes to PCIe 4.0

Gearing Up for PCIe 4.0 Electrical Compliance Test

Figure 1: A key element in PCIe 4.0
compliance test is a high-bandwidth,
real-time oscilloscope (shown is the
Teledyne LeCroy LabMaster 10Zi-A)

Armed with some of the background information and history on PCIe 4.0 electrical compliance testing, we're now ready to look at just what it takes in terms of test equipment to determine compliance for a PCIe 4.0 device. With the increase in data-transfer rate from 8 Gb/s in PCIe 3.0 to 16 Gb/s in PCIe 4.0, so too have the test equipment requirements advanced.