Automotive Ethernet Compliance: Tests in Detail (Part II)

Figure 1: Testing transmitter timing master jitter
entails creating a track of TIE measurements

We've begun our deep dive into the subject of Automotive Ethernet compliance testing. In our last post, we covered the first two of seven tests: maximum transmitter output droop and transmitter clock frequency. Let's now look at transmitter timing jitter in master and slave modes.

The History of Jitter (Part V)

Figure 1: Applying PLLs for clock-data recovery is not
unlike tapping your feet to the beat of music

A milestone in the history of jitter measurement came in the 1990s with receivers that could reveal the slowly varying component of jitter that became evident in time-interval error (TIE) tracks. That led to the advent of using phase-locked loops (PLLs) for clock-data recovery. In turn, PLLs opened new horizons in jitter analysis.

The History of Jitter (Part IV)

Figure 1: An example of a time-interval error track

In the previous installment in this series on the history of jitter, we'd reached the cusp of the new millennium. The in-vogue methodology for jitter analysis of the day was using edge crossing-point data in the form of a histogram and fitting Gaussian functions to the tails of the plot. But tail fitting, as we well know, isn't for the faint of heart. How would test methodologies move forward to surmount that hurdle?

Measuring Time-Interval Error in Serial Data Waveforms

Figure 1: The first step in quantifying jitter is to
determine measured times of arrival for bit transitions

A recent post covered some of the reasons why one might want to measure jitter. In design and debug of serial-data channels, jitter is among the most prevalent causes of unacceptable bit-error rates (BERs). In that earlier post, we looked at the physical phenomenon of jitter and why it wreaks the havoc that it does. In the present installment, we will look in broad terms at how jitter is measured and quantified.