Decision Feedback Equalization

Figure 1: DFE filter output is based on
a linear combination of previous bit
decisions

In debugging high-speed serial links, one must be cognizant of various forms of equalization that might be used in the link to compensate for signal degradation in the channel. Inter-symbol interference (ISI), attenuation, impedance mismatches, and insertion losses can all contribute to this loss of signal quality. To combat these effects, designers implement techniques such as continuous time linear equalization and feed-forward equalization.

Feed-Forward Equalization

Figure 1: FFE creates a number of delayed versions of the
input signal that are then added back to the signal with
proper weights

In addition to continuous time linear equalization (CTLE), another means of improving signal quality at the receiver end of a high-speed serial data link is known as feed-forward equalization (FFE). In terms of implementation, FFE is not unlike the pre-emphasis filtering that is done on the transmitter side. An FFE implementation looks for all intents and purposes like a digital finite impulse response (FIR) filter.

Continuous Time Linear Equalization

Figure 1: A CTLE implementation at the receiver end of a
serial-data channel seeks to boost higher frequencies while
not boosting noise any more than necessary

We've been looking at the broad topic of debugging high-speed serial links, and in that context, we're also touching on ways to improve signal performance on the receiver side. One of those ways is to implement continuous time linear equalization (CTLE).

Introduction to Channel Equalization

Figure 1: Transmit pre-emphasis pre-distorts signals
in anticipation of the channel's effects

A number of factors can cause degradation of performance in a high-speed serial data link. Among them are inter-symbol interference (ISI) jitter, attenuation, reflections due to impedance mismatches, and insertion losses, to name a few. But fear not: There are techniques one may use to compensate for these losses known as equalization. We'll review the basics of channel equalization in today's post.

An Under-The-Hood View of PCIe 3.0 Link Training (Part II)

Figure 1: A diagrammatic view of the
PCIe 3.0 dynamic link training process

Our last post in this series began examining the recovery.equalization process of PCIe 3.0 dynamic link training, beginning with Phases 0 and 1 of the process (Figure 1). Next, we will move on to take a closer look at Phases 2 and 3, where we'll see what can happen with devices in which the algorithms are not up to par. Namely, issues such as packet errors, dropped packets, and link retraining at lower data rates than 8 Gb/s.

PCIe 4.0 Receiver Link-Equalization Testing (Part II)

Figure 1: Working out the optimal combination of Tx emphasis
presets and receiver CTLE settings

As may be apparent from our previous post on PCIe 4.0 receiver link-equalization testing, this part of the PCIe 4.0 compliance tests is somewhat involved. When we left off last time, we were in the midst of receiver calibration, looking to ensure that the test-signal eye is as closed as possible without violating the specification limits.

An Under-the-Hood View of PCIe 3.0 Link Training (Part I)

Figure 1: An overview of the elements of PCIe 3.0
dynamic link equalization

Now that we've looked at the basics of PCIe 3.0 dynamic link equalization and at some of the particulars of de-emphasis and preshoot, it's time to dive a little deeper into what actually happens in the link training process. It all happens in the blink of an eye but there's enough going on to warrant some dissection.

PCIe 3.0 Dynamic Link EQ: De-Emphasis, Preshoot, Cursors, and Presets

Figure 1: De-emphasis, a key transmit-side equalization
technique for PCIe 3.0, boosts high-frequency content

In an earlier post, we looked at some of the basics of dynamic link equalization for PCIe 3.0, and in particular the reasons why it's not only necessary but mandated by the PCI-SIG for compliance testing. Essentially, the boost in data rates from 5 GT/s in PCIe 2.0 to 8 GT/s in PCIe 3.0 wreaked havoc in terms of signal integrity in the channel. The solution is found in equalization both before (TxEQ) and after (RxEQ) the channel.

The Hows and Whys of PCIe 3.0 Dynamic Link Equalization

Figure 1: SI problems are the root cause for
dynamic link equalization in PCIe 3.0

If you're designing a computer peripheral these days, chances are that you'll use the Peripheral Component Interconnect Express (PCIe) protocol for communication between the device and the host system. With the emergence of PCIe, a bunch of older bus standards were kicked to the curb. PCIe itself became the basis for more specialized standards, most notably ExpressCard for laptop expansion cards and SATA Express for storage interfaces.