The Hows and Whys of PCIe 3.0 Dynamic Link Equalization

Figure 1: SI problems are the root cause for
dynamic link equalization in PCIe 3.0

If you're designing a computer peripheral these days, chances are that you'll use the Peripheral Component Interconnect Express (PCIe) protocol for communication between the device and the host system. With the emergence of PCIe, a bunch of older bus standards were kicked to the curb. PCIe itself became the basis for more specialized standards, most notably ExpressCard for laptop expansion cards and SATA Express for storage interfaces.

The current version of the PCIe specification, 3.0, brought some notable improvements over PCIe 2.0. Bit rates rose from 5 GT/s to 8 GT/s (effective bit rates of 4 Gb/s per lane and 7.88 Gb/s per lane, respectively). However, for products to exhibit compliance to the spec and garner the coveted PCIe logo, receiver testing, which was deemed "informative" for PCIe 2.0, became a requirement in PCIe 3.0.

Perhaps the biggest change from PCIe 2.0 to PCIe 3.0 other than the bit rate was the requirement for dynamic link equalization. The main reason why dynamic link equalization becomes so critical in PCIe 3.0 is because even though the bit rate was bumped up, the specification for the transmission path, i.e. connectors, remained constant. In fact, the PCIe transmission path spec hasn't changed since PCIe 1.0, when the bit rate was 2.5 GT/s. At that speed, little emphasis was placed on signal integrity concerns.

Figure 2: Making PCIe 3.0 work requires equalizers
at the transmit and receive ends of the channel

Along comes PCIe 3.0 and its 8-Gb/s bit rate; now things are very different from a signal-integrity point of view. Connectors, PC boards, and other path elements are generally built using lossy materials. Now add to the mix a relatively long transmission path replete with connectors and vias, and things start to get ugly in the physical layer. The nice, clean, open eye diagram you had at the output of one transceiver, perhaps mounted on the host system's motherboard, is in bad shape by the time it reaches the endpoint, which might be a storage device or graphics card (Figure 1). With propagation, the signal degrades and the eye closes like it'd been punched by Mike Tyson. A receiver sampling that signal would display a bit-error-rate (BER) that would never make it out of the Gold Suite at a PCIe workshop.

The answer to this conundrum is equalizers. With signal equalizers either before, after, or (most typically) at both ends of the channel, the anomalies in the signal are compensated for and the channel hits the PCI-SIG's required bit-error rate of at least 10^-12 (Figure 2). Transmit-side equalization (referrred to as TxEQ) comes in the form of de-emphasis and preshoot , while receive-side equalization (known as RxEQ) takes the form of continuous-time linear equalization (CTLE) and decision feedback equalization (DFE).

In principle, what happens to degrade PCIe signal integrity is that the channel acts on the signal as if it were a low-pass filter by attenuating the higher-frequency components. The equalization does the inverse by boosting those high-frequency components.

Next time, we'll look more closely at these equalization techniques and how they function.