How Equalization Works in 10x Passive Probes

Figure 1: The adjustable equalization circuit on the oscilloscope
end of the coaxial cable compensates for the 10x passive
probe's inherent low-pass filter characteristics

We've been discussing 10x passive probes and their inner workings; our last post covered all the ways in which a 10x passive probe is apt to be a liability. They'd be basically unusable for any measurements at all but for one attribute: their equalization circuit (Figure 1). Without it, the 10x passive probe makes a pretty good low-pass filter, but the equalization circuit counters that with a high-pass filter to balance things out.

Decision Feedback Equalization

Figure 1: DFE filter output is based on
a linear combination of previous bit
decisions

In debugging high-speed serial links, one must be cognizant of various forms of equalization that might be used in the link to compensate for signal degradation in the channel. Inter-symbol interference (ISI), attenuation, impedance mismatches, and insertion losses can all contribute to this loss of signal quality. To combat these effects, designers implement techniques such as continuous time linear equalization and feed-forward equalization.

The History of Jitter (Part V)

Figure 1: Applying PLLs for clock-data recovery is not
unlike tapping your feet to the beat of music

A milestone in the history of jitter measurement came in the 1990s with receivers that could reveal the slowly varying component of jitter that became evident in time-interval error (TIE) tracks. That led to the advent of using phase-locked loops (PLLs) for clock-data recovery. In turn, PLLs opened new horizons in jitter analysis.

PCIe 3.0 Dynamic Link EQ: De-Emphasis, Preshoot, Cursors, and Presets

Figure 1: De-emphasis, a key transmit-side equalization
technique for PCIe 3.0, boosts high-frequency content

In an earlier post, we looked at some of the basics of dynamic link equalization for PCIe 3.0, and in particular the reasons why it's not only necessary but mandated by the PCI-SIG for compliance testing. Essentially, the boost in data rates from 5 GT/s in PCIe 2.0 to 8 GT/s in PCIe 3.0 wreaked havoc in terms of signal integrity in the channel. The solution is found in equalization both before (TxEQ) and after (RxEQ) the channel.

The Hows and Whys of PCIe 3.0 Dynamic Link Equalization

Figure 1: SI problems are the root cause for
dynamic link equalization in PCIe 3.0

If you're designing a computer peripheral these days, chances are that you'll use the Peripheral Component Interconnect Express (PCIe) protocol for communication between the device and the host system. With the emergence of PCIe, a bunch of older bus standards were kicked to the curb. PCIe itself became the basis for more specialized standards, most notably ExpressCard for laptop expansion cards and SATA Express for storage interfaces.