Some More PCIe 3.0 Test Examples (Part II)

Figure 1: This shows how a PeRT 3 state-machine log can be invaluable
in diagnosing timeouts in requests for presets

Continuing on from our last post, let's look at some more examples of common PCIe 3.0 test scenarios and how a well-equipped PCIe 3.0 testbench would approach them. Recall, if you will, that such a testbench would comprise a real-time digital oscilloscope of suitable bandwidth (such as Teledyne LeCroy's SDA830Zi-B oscilloscope), a protocol-enabled receiver tester (such as Teledyne LeCroy's PeRT 3 Phoenix System), and software that enables simultaneous, correlated views of the protocol and physical layers (such as Teledyne LeCroy's ProtoSync software).

An Under-The-Hood View of PCIe 3.0 Link Training (Part II)

Figure 1: A diagrammatic view of the
PCIe 3.0 dynamic link training process

Our last post in this series began examining the recovery.equalization process of PCIe 3.0 dynamic link training, beginning with Phases 0 and 1 of the process (Figure 1). Next, we will move on to take a closer look at Phases 2 and 3, where we'll see what can happen with devices in which the algorithms are not up to par. Namely, issues such as packet errors, dropped packets, and link retraining at lower data rates than 8 Gb/s.

An Under-the-Hood View of PCIe 3.0 Link Training (Part I)

Figure 1: An overview of the elements of PCIe 3.0
dynamic link equalization

Now that we've looked at the basics of PCIe 3.0 dynamic link equalization and at some of the particulars of de-emphasis and preshoot, it's time to dive a little deeper into what actually happens in the link training process. It all happens in the blink of an eye but there's enough going on to warrant some dissection.

PCIe 3.0 Dynamic Link EQ: De-Emphasis, Preshoot, Cursors, and Presets

Figure 1: De-emphasis, a key transmit-side equalization
technique for PCIe 3.0, boosts high-frequency content

In an earlier post, we looked at some of the basics of dynamic link equalization for PCIe 3.0, and in particular the reasons why it's not only necessary but mandated by the PCI-SIG for compliance testing. Essentially, the boost in data rates from 5 GT/s in PCIe 2.0 to 8 GT/s in PCIe 3.0 wreaked havoc in terms of signal integrity in the channel. The solution is found in equalization both before (TxEQ) and after (RxEQ) the channel.

The Hows and Whys of PCIe 3.0 Dynamic Link Equalization

Figure 1: SI problems are the root cause for
dynamic link equalization in PCIe 3.0

If you're designing a computer peripheral these days, chances are that you'll use the Peripheral Component Interconnect Express (PCIe) protocol for communication between the device and the host system. With the emergence of PCIe, a bunch of older bus standards were kicked to the curb. PCIe itself became the basis for more specialized standards, most notably ExpressCard for laptop expansion cards and SATA Express for storage interfaces.