Signal and Power Integrity Tutorial: Measuring Clock Jitter Sensitivity to Power Rail Noise, Pt. 2

Figure 1. 400 mVpp oscillation on the power trace
is due to 48 MHz clock noise.

In Part 1, we used a function generator to create a power source with a known perturbation. Seeing that the noise on the power rail and the clock period were synchronous when we observed both traces together using a WavePro HD oscilloscope, we knew that there was a clear relationship between the two to be further investigated. Now, we're ready to examine more closely how the clock jitter responds to voltage variations on the power rail.

Signal and Power Integrity Tutorial: Measuring Clock Jitter Sensitivity to Power Rail Noise, Part 1

Figure 1. Voltage variations on the power rail
shown in the same grid as the clock period track
(jitter track). These waveforms are the basis of
the clock jitter sensitivity measurement. The
inverse relationship between the jitter track and
the power trace shows that the clock
is sensitive to variations in rail voltage.

In a previous post, we described A Robust Method for Measuring Clock Jitter with Oscilloscopes as variation in a clock signal’s period. Clock jitter is characterized by the standard deviation (sdev) of the clock period measurement. The track function of the clock period sdev shows us the variations in jitter over time, synchronous with the waveform source. 

In this post and the next, we’ll show how to make use of the clock period track function to match jitter variations to possible sources of jitter, in particular to voltage variations on the clock power rail. The offset voltage of a function generator powers a clock signal source. By creating a known variation in the function generator output, we can match that to the resulting clock jitter to calculate the clock jitter sensitivity to rail voltage changes. A known clock jitter sensitivity value can help you predict how a design will respond to rail voltage changes.

Signal and Power Integrity Tutorial: A Robust Method for Measuring Clock Jitter with Oscilloscopes

Figure 1. Clock jitter measured as a variation
of clock signal absolute period.

Clock jitter is the variation of a clock signal’s frequency or period. Either measurement carries the same information, but the period measurement is a simple time interval measurement easily performed using a real-time oscilloscope. If we have a robust way of measuring clock jitter, we have the basis for measuring the clock signal’s sensitivity to other features in the environment that can affect the period. Voltage noise on the power rail is just one external force that can affect clock jitter, which we'll show you how to measure in a future post.

In this post, we’ll demonstrate a robust method for measuring clock jitter using an example from Dr. Eric Bogatin’s webinar, “The Impact of Power Rail Noise on Clock Jitter.”  

The clock in our examples is a 5-stage ring oscillator which generates a square wave signal between 10 and 66 MHz. The test instrument is a WavePro HD 12-bit, 4-Ch, 8 GHz, 20 GS/s, 5 Gpts oscilloscope with 60 fs sample clock jitter.

In the process, we make a series of oscilloscope sample clock tests and timebase adjustments as  consistency checks. While measuring jitter is less about absolute accuracy than about the relative precision of measuring the time interval from cycle to cycle, a fundamental part of that is ensuring the absolute accuracy of the oscilloscope’s timebase.

Transmission Lines (Part II): More on Bandwidth vs. Rise Time

Figure 1: In the frequency domain (right), a near-ideal
square wave displays predictable 1/f amplitude dropoff

We began this series about transmission lines by thinking about some pertinent principles and relationships that can help form our thinking about the topic. In particular, we'd covered the relationship between bandwidth and rise time and why we have this rule of thumb that says that bandwidth can be estimated using 0.35/10-90% rise time.

Making On-Die Power-Rail Measurements (Part III)

Figure 1: This screen capture shows
the idle-state conditions

Having reviewed the test setup for on-die power-rail testing and our expectations of what the tests should show us, let's walk through the measurements and look over the results. We'll also note whether our results align with our expectations or are outside of those expectations.

Making On-Die Power-Rail Measurements (Part II)

Figure 1: When switching from low to
high, PDN noise flows from the Vdd
rail through to the Vss rail

Now that we're ready to begin some on-die power-rail measurements, it's a good idea to step back for a moment and anticipate what these measurements should show us. What actually happens on the die when CMOS gates are switching on and off? What should we expect to see on the on-die power rails? And what happens at the clock edges?

Testing the DDR Memory Interface's Physical Layer (Part I)

Figure 1: Clock, strobe, and data are
three critical signals in DDR test

In an earlier post, we took a brief tour through what constitutes a DDR memory interface: clock, command, address, and strobe+data lines linking a memory controller and an array of DRAM memory ICs. Next, we'll examine what DDR interface testing is all about, concentrating primarily on the physical layer.

Fundamentals of the DDR Memory Interface

Figure 1: A representative test setup
for physical-layer DDR testing

Double data-rate (DDR) memory has ruled the roost as the main system memory in PCs for a long time. Of late, it's seeing more usage in embedded systems as well. Let's look at the fundamentals of a DDR interface and then move into physical-layer testing (Figure 1).