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02 May 2022

Measuring Clock Jitter Sensitivity to Power Rail Noise, Pt. 1

Figure 1. Voltage variations on the power rail
shown in the same grid as the clock period track
(jitter track). These waveforms are the basis of
the clock jitter sensitivity measurement. The
inverse relationship between the jitter track and
the power trace shows that the clock
is sensitive to variations in rail voltage.

In a previous post, we described A Robust Method for Measuring Clock Jitter with Oscilloscopes as variation in a clock signal’s period. Clock jitter is characterized by the standard deviation (sdev) of the clock period measurement. The track function of the clock period sdev shows us the variations in jitter over time, synchronous with the waveform source. 

In this post and the next, we’ll show how to make use of the clock period track function to match jitter variations to possible sources of jitter, in particular to voltage variations on the clock power rail. The offset voltage of a function generator powers a clock signal source. By creating a known variation in the function generator output, we can match that to the resulting clock jitter to calculate the clock jitter sensitivity to rail voltage changes. A known clock jitter sensitivity value can help you predict how a design will respond to rail voltage changes.

As in our previous post, the clock is a 5-stage ring oscillator based on the the 74AC14 hex inverter, powered by a 5 V rail. The test instrument is a WavePro HD 12-bit, 4-Ch, 8 GHz, 20 GS/s, 5 Gpts oscilloscope with 50 ps time resolution and 60 fs intrinsic sample clock jitter, which is used to measure a square wave clock signal between 10 and 66 MHz. For this experiment, we also use a 5 V DC clean power source to test what our clock jitter is with an “ideal” rail, and a function generator to generate a perturbing signal that will put noise on our 5 V power rail so we can test how the clock jitter responds to it.

1. Measure Clock Jitter Using a Clean Power Source

Figure 2. Measuring clock period with
clock powered by a clean source.
First, we connect the clock signal source to the clean 5 V power source and to our test oscilloscope. With the clock channel set to 50 Ω input termination, 1 V/div vertical scale, timebase of 5 ns/division and a 50% Edge trigger, we measure the clock signal rise time, frequency and period. Figure 2 shows the period of the clock signal (P3) when measured with a stable power source. The period sdev is our figure of merit for the clock signal jitter.

2. Create a Power Source with a Known Voltage Perturbation

Next, we connect the output of the function generator to another oscilloscope input channel. In our examples, C2 (pink) is the clock signal and C3 (blue) is the function generator output. 

Figure 3. Function generator output square wave.
The function generator input channel is set to 1 MΩ input termination and 200 mV/div with 5 V offset, while the timebase is switched to 20 µs/div with a fixed sample rate of 20 GS/s.

The function generator is set to output a 200 mV peak-to-peak, 10 kHz square wave with a 5 V offset. We connect the function generator’s sync output to the oscilloscope’s Ext. input so that we can set a 50% Edge trigger on the function generator output. Figure 3 shows the function generator output simulating a 5 V power rail with a small square wave perturbation.

3. Connect the Perturbed Power Source to the Clock 

Figure 4. The function generator output connected
to the clock. Note the drop in voltage.
While maintaining the connection from the function generator to the oscilloscope so the waveform remains on display, we use a coaxial tee adaptor to replace the stable power input to the clock with the function generator output. (NOTE: From here on, we’ll refer to the function generator output as the power source and its trace as the power trace.)

Our power trace is now off the screen, so we readjust the V/div and Offset to get it back on the screen as shown in Figure 4. The Mean measurement parameter (P4 on C3) reads the mean amplitude of the power source.

You may wonder why the mean output level has dropped from 5 V to 3.3 V. When the power source is connected to the clock, the voltage decreases significantly, due to the loading of the power source by the ring oscillator. 

Figure 5. A 400 mVpp oscillation related to the
clock appears on the power trace.
We adjust the offset of the power source until it is again 5 V, and set a Vertical Scale of 100 mV/div, and we can see a visible 400 mV peak-to-peak oscillation on the trace, as shown in Figure 5.

4. Investigate the Relationship Between the Clock and Power Source

Since this oscillation happened after the power source was connected to the clock, and not before, it is obviously somehow related to the clock. As it happens, the ring oscillator load changes with every output state change, causing the oscillation.

Figure 6. The noise on the power rail and the
clock output are synchronous. The 48 MHz
frequency noise is from the clock.
We switch our 50% Edge trigger to the clock signal and display both the clock signal trace and the power trace on the same grid, zoomed until we can see individual cycles of the waveforms. If the waveforms are synchronous, as shown in Figure 6, we can verify that the oscillation in the power trace is most probably due to the effects of the clock.  

Now that we know we have a clear relationship between the clock frequency and the power rail noise, in the next post, we'll show how to calculate the effect of the rail noise on the clock jitter.

Want to try this with your clock source? Download our step-by-step tutorial, Measuring Clock Jitter Sensitivity to Power Rail Noise.

You can also watch Dr. Eric Bogatin demonstrate in the on-demand webinar, “The Impact of Power Rail Noise on Clock Jitter.”

See also:

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