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You need to test, we're here to help.

24 January 2018

Making On-Die Power-Rail Measurements (Part III)

This screen capture shows the idle-state conditions
Figure 1: This screen capture shows
the idle-state conditions
Having reviewed the test setup for on-die power-rail testing and our expectations of what the tests should show us, let's walk through the measurements and look over the results. We'll also note whether our results align with our expectations or are outside of those expectations.

First, let's look at the MCU's idle state with only the low-current trigger I/O functionality in play (Figure 1). At top is the quiet-high line (Vcc on-die) while at bottom is the quiet-low line (Vss on-die), both relative to the voltage on the demo board. So this effectively represents the voltage noise through the power-distribution network (PDN) on the die, and through the package as well, to the ground plane on the board where there's low impedance in the return path.

The center yellow trace in Figure 1 is the single pin 8 that we're using as an oscilloscope reference trigger. It is drawing a small amount of current; it's a 500-Ω load with a 5-V source, so it's drawing about 10 mA when it switches on.

Power-supply noise appears on the demo board
Figure 2: Power-supply noise appears
on the demo board
Some points of interest about the pin-8 signal: Rise time is 3.2 ns, which give us the rise time of the output drivers in this particular Atmel MCU. Pulse width measures 64 ns; recall from an earlier post that the clock frequency is 16 MHz, which makes this one clock cycle. The I/O switches on the leading edge and latches on the falling edge.

Now for the noise signals. Note that we see voltage noise on the power rail when PDN current sloshes onto the rising clock edge. At the falling edge you see the transient current, and comparing the two, you can clearly see the asymmetry we expected. The rising edge, when the gate switches, has a lot more current draw and more voltage drop than the falling edge when the gate latches. Before and after the switching event, the voltage noise in the idle state reflects other activities of the MCU such as looking for interrupts and the like.

Also, note that when the output switches from high to low, there's a collapse in the power rail and a recovery with some overshoot. That's the impact on the power rail of that small 10-mA switching current. The noise is evident on the quiet line as well as some ground bounce.

The effects of I/O toggling appear in this screen capture
Figure 3: The effects of I/O toggling
appear in this screen capture
That's what's happening on the die. What about the printed-circuit board? Figure 2 shows us the board-level Vcc supply relative to ground. At top is a 5-V USB laptop port that's powering the MCU, and it displays the typical signature of a switch-mode power supply. The power supply has a switching frequency of about 50 kHz. Noise is 30 mV pk-pk. At bottom is the low-dropout (LDO) regulator on the board, which is powered by an external 9-V DC supply. That supply is pretty noisy but the LDO filters a lot of that out. The voltage noise here is a scant 2 mV pk-pk, and this is where the signal-to-noise ratio matters a lot.

Next, let's see what happens when we start other I/Os toggling on and off. Shown in Figure 3 is the voltage noise on the die (quiet-high line/Vcc at top in white), and one of the other I/Os switching (V_I/O at center in purple). As this I/O switches, we see more current flow in the quiet-low line/Vss (at bottom in blue) and some negative ground bounce. When that current switches out, a large amount of current flows through the ground return, which is the inductance on the return in the package. Everything on the die that shares the Vss line sees that voltage noise.

On the power rail itself (Vcc), we can see the clock noise in the left-hand portion of the trace before the I/O switches on. When the switching occurs, we can see a very large voltage drop, as well as more voltage noise. It's a drop of about 300 mV caused by several I/Os switching at once (only one of which is seen in the screen capture of Figure 3). When V_I/O switches from high to low, there's a voltage bounce in Vss of about 200 mV.

Here's a bigger-picture view of the voltage noise on the die and on the board with more I/O activity
Figure 4: Here's a bigger-picture view
of the voltage noise on the die and on
the board with more I/O activity
Meanwhile, on the board (Vcc-board at center in red), very little noise is observable, with a voltage drop of less than 30 mV. It's the transient currents happening on the die that are the aggressors in this scenario. The LDO on the board is similarly affected very little, because the package-lead inductance filters out a lot of the noise.

Lastly, let's look at the waveforms when a bunch of I/Os are switching. We'll use a longer on-time for the I/Os and have the time base zoomed out for a bigger picture (Figure 4). At top in green, we see the quiet-high/Vcc line on the die. With our vertical scale set at 200 mV/div, this is a voltage drop of almost 600 mV, from 5.1 V to 4.5 V. You can see a bit of a transient signature in the trace as well as evidence of a large low-frequency or DC component. This indicates that there's a good amount of IR drop in the on-die PDN.

Meanwhile, the voltage on the board (red trace) is much more well behaved with a drop of just 12 mV and a quick 2-μs recovery. As we'd expect, we see a critically damped response. The voltage recovers because the sense line pulls the voltage back up, and because the board's PDN doesn't exhibit as much of an IR drop as the die's PDN. There's a huge difference between on-die voltage noise and on-board voltage noise. There's 250 mV of transient ground bounce noise caused by a large current switching through the package inductance.

In these posts on on-die power-rail measurements, we've seen how we can use quiet-high and quiet-low I/O lines as sense lines for taking these measurements, and how to use a 450-Ω series load as a 10X probe multiplier to lightly load an I/O pin as an oscilloscope trigger. We've found that the main source of voltage noise on the board is the IR drop on the die due to package lead inductance and ground bounce. Keep in mind when making these sorts of measurements that the voltage noise on the die is not the same as the voltage noise on the board.

Previous posts in this series:

Understand RF Pickup When Measuring Power Rails
How 10X Attenuating Probes Kill Signal-To-Noise Ratio
Bandwidth vs. Current Load in Power-Rail Measurements
Power-Rail Noise: Small Signal, Big DC Offset
Setting the Stage for On-Die Power-Rail Measurements
Measuring Shared On-Die Power Rails
Making On-Die Power-Rail Measurements (Part I)
Making On-Die Power-Rail Measurements (Part II)

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