Signal and Power Integrity Tutorial: Power Rail Probing for Rail Compression

Figure 3. Equivalent circuit of a typical CMOS I/O
showing the connection from the on-die rails
and the board-level test points.

By Prof. Eric Bogatin,
Teledyne LeCroy Fellow

Excerpted by permission from the Signal Integrity Journal article, Measuring Only Board-level Power Rail Noise May Be Misleading

Continued from Part 1.

Measuring Rail Compression on the Die

In most applications, we do not have access to the bare die when the chip is assembled on the circuit board. If the IC package has not been instrumented with special pass-through features connecting the rails on the die to board pins, we have to rely on a special trick. [The use of a quiet HIGH and quiet LOW]

When the I/Os of a chip all share the same power and ground rails, which is often the case in small microcontroller devices, designated I/Os can be used as sense lines to measure externally the power rails on the die.

Signal and Power Integrity Tutorial: How PDN Design Affects Board-level Noise

Figure 1. Oscilloscope traces resulting from 
measuring a 3.3. V power rail with a 10x probe
versus a coaxial connection, with an
adjacent 10x probe acting as an RF antenna.

By Prof. Eric Bogatin,
Teledyne LeCroy Fellow

Excerpted by permission from the Signal Integrity Journal article, Measuring Only Board-level Power Rail Noise May Be Misleading

In our blog, we’ve presented a lot about the impact of the interconnect on oscilloscope measurements, and how where you probe can be as important as how you probe. This article is an excellent demonstration of those very principles.

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Power rail measurements are important because they can identify potential sources of noise before they become a problem. However, measuring only the power rail noise at the board-level may be a misleading indication of the noise the die actually sees. 

Best Practices for Power Integrity Measurements

Measuring a power rail on a board seems like a simple task. Like all measurements, it is easy to get a waveform on the oscilloscope’s screen, but it is difficult to have confidence you have eliminated the measurement artifacts and have a realistic measure of the actual signal present.

Making On-Die Power-Rail Measurements (Part II)

Figure 1: When switching from low to
high, PDN noise flows from the Vdd
rail through to the Vss rail

Now that we're ready to begin some on-die power-rail measurements, it's a good idea to step back for a moment and anticipate what these measurements should show us. What actually happens on the die when CMOS gates are switching on and off? What should we expect to see on the on-die power rails? And what happens at the clock edges?

The Power Integrity Measurement Mindset

Figure 1:  The holistic view
of power integrity

In kicking off a series of posts on power integrity measurements, it might be helpful to start with some thoughts on the mindset, or approach, that one should take in the endeavor. Power integrity is best approached holistically, with an eye toward each of the paths energy may take throughout a system.

Back to Basics: The Fundamentals of Power

Figure 1: 45% of worldwide power
consumption fuels motors

Ask any number of engineers to define "power" and you'll get any number of answers, and none of them would necessarily be wrong. Sometimes it's just a matter of perspective.