Signal and Power Integrity Tutorial: Power Rail Probing for Rail Compression

Figure 3. Equivalent circuit of a typical CMOS I/O
showing the connection from the on-die rails
and the board-level test points.

By Prof. Eric Bogatin,
Teledyne LeCroy Fellow

Excerpted by permission from the Signal Integrity Journal article, Measuring Only Board-level Power Rail Noise May Be Misleading

Continued from Part 1.

Measuring Rail Compression on the Die

In most applications, we do not have access to the bare die when the chip is assembled on the circuit board. If the IC package has not been instrumented with special pass-through features connecting the rails on the die to board pins, we have to rely on a special trick. [The use of a quiet HIGH and quiet LOW]

When the I/Os of a chip all share the same power and ground rails, which is often the case in small microcontroller devices, designated I/Os can be used as sense lines to measure externally the power rails on the die.

Signal and Power Integrity Tutorial: How PDN Design Affects Board-level Noise

Figure 1. Oscilloscope traces resulting from 
measuring a 3.3. V power rail with a 10x probe
versus a coaxial connection, with an
adjacent 10x probe acting as an RF antenna.

By Prof. Eric Bogatin,
Teledyne LeCroy Fellow

Excerpted by permission from the Signal Integrity Journal article, Measuring Only Board-level Power Rail Noise May Be Misleading

In our blog, we’ve presented a lot about the impact of the interconnect on oscilloscope measurements, and how where you probe can be as important as how you probe. This article is an excellent demonstration of those very principles.

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Power rail measurements are important because they can identify potential sources of noise before they become a problem. However, measuring only the power rail noise at the board-level may be a misleading indication of the noise the die actually sees. 

Best Practices for Power Integrity Measurements

Measuring a power rail on a board seems like a simple task. Like all measurements, it is easy to get a waveform on the oscilloscope’s screen, but it is difficult to have confidence you have eliminated the measurement artifacts and have a realistic measure of the actual signal present.

Fundamentals of Power Integrity: Mutual Aggressors and Rail Transient Response Measurement

Fig 1. Rail droop in response to a load step is
a typical case of mutual aggressors in a PDN.

A third type of noise found in PDNs is what we call mutual aggressors, which is crosstalk coupling from one component of the PDN onto another.

An obvious example is a load step in the PDA, where something in the system being turned on pulls current from the VRM that supplies a rail. In Figure 1, you can see how the output voltage of the VRM supplying a 1 V rail droops in response to a load step before it recovers. This is still noise: it is a signal variation that we're not expecting and don't want.

We want to be able to characterize that noise, because too much droop could affect the operation of other components that are already consuming power from that device.

In order to do so, we’re going to measure the rail transient response to the load application. We need only look at two signals: the voltage and the current on the rail of interest. Figure 1 shows the voltage on C5 (the green trace) and the current on C8 (the orange trace).

Fundamentals of Power Integrity: Board Pollution

Figure 1. "Pollution" occurring on PDN traces.

Board pollution is noise occurring on the packages and interconnects (traces and planes) that carry current from the VRMs to the consumer devices.
One place it can originate is from the VRM itself, for example, with the switching noise the VRM generates (Figure 1). That can be a real concern if the board capacitance means you have a resonance around the switching frequency that would act as an amplifier for the switching noise and cause all kinds of problems with other devices on the board.

Fundamentals of Power Integrity: Self-aggression Noise

Fig. 1: VRM-switching noise is a self aggressor that can be
identified because it is synchronous with the PWM clock. 

Self-aggression noise is so-called because it is inflicted by a component onto itself through its normal operation; nothing else in the system is affecting it. When we look for this, we want to ensure the system is in a steady state, in a place where the noise environment is fairly clear (e.g., the device is on an evaluation board).

An example of self-aggression would be VRM-switching noise. Figure 1 shows ripple on a 900 millivolt rail (yellow trace) at a time when no load is present. One of the things that tells us this is switching noise is that it is synchronous to the PWM clock (red trace). Ripple that is synchronous with the switching clock is a typical figure of merit for identifying switching noise.

Fundamentals of Power Integrity: Characterizing PDN Noise

Figure 1. Noise tolerances for embedded system
components are becoming ever tighter.

Power integrity concerns maintaining the quality of power from generation to consumption in an embedded system. “Good” power integrity could be defined as having noise levels that are within tolerance. This short series will focus on characterizing noise on your power delivery network (PDN), with the goal of knowing where you must adjust your design to meet those tolerances.

Why do we care about voltage rail noise? As electronic designs strive for ever lower power consumption, power rails already carry very low voltages, often 1 V or less. Components like RF receivers, ADCs and DACs can be affected by noise of less than 1% of the rail value (Figure 1). This means noise tolerances can be as tight as single-digit millivolts, which is why power integrity takes up considerable validation time in labs.

Making On-Die Power-Rail Measurements (Part III)

Figure 1: This screen capture shows
the idle-state conditions

Having reviewed the test setup for on-die power-rail testing and our expectations of what the tests should show us, let's walk through the measurements and look over the results. We'll also note whether our results align with our expectations or are outside of those expectations.

Making On-Die Power-Rail Measurements (Part II)

Figure 1: When switching from low to
high, PDN noise flows from the Vdd
rail through to the Vss rail

Now that we're ready to begin some on-die power-rail measurements, it's a good idea to step back for a moment and anticipate what these measurements should show us. What actually happens on the die when CMOS gates are switching on and off? What should we expect to see on the on-die power rails? And what happens at the clock edges?

Making On-Die Power-Rail Measurements (Part I)

Figure 1: Our test setup for the
on-die measurement examples

Our exploration of on-die power-rail measurements has brought us to the point of demonstrating some examples of these measurements. As noted in the prior post, we will use an Atmel 328 microcontroller demo board, prepared with firmware to control it explicitly for our purposes, and with coaxial cable in place on the bottom of the board to serve as transmission lines for our signals of interest.

Measuring Shared On-Die Power Rails

Figure 1: This schematic represents the signal paths
in typical, general-purpose I/Os

If you're taking power-rail measurements on a semiconductor die that is appropriately instrumented with sense lines and a direct connection to the die's core PDN, you're in pretty good shape. But what if that's not the case? If the die's I/O power rails are shared by the core power rails, here's a way to get your core power-rail measurements anyway.

Setting the Stage for On-Die Power-Rail Measurements

Figure 1: Measuring on-die Vdd rail noise requires
a suitably instrumented die and package

Armed with a suitable oscilloscope and active voltage-rail probe, you're now ready to make some power-rail measurements on a semiconductor die. Of course, making measurements on a die is a little different than making measurements on a printed-circuit board. This is where careful design-for-test at the die level comes in, because the chip, its packaging, and the board on which it will be mounted must be instrumented so as to make the on-die measurements possible.

The Power Integrity Measurement Mindset

Figure 1:  The holistic view
of power integrity

In kicking off a series of posts on power integrity measurements, it might be helpful to start with some thoughts on the mindset, or approach, that one should take in the endeavor. Power integrity is best approached holistically, with an eye toward each of the paths energy may take throughout a system.