The Evolution of In-vehicle Network Architectures

The drive for fuel-efficient and safer vehicles opened the door to electronic control in vehicles, which in turn led to the deployment of In-vehicle Networks (IVN).  IVNs have become the backbone of modern vehicles. The volume of data flowing through these networks is increasing exponentially with demands for electric vehicles, advanced driver assistance systems (ADAS), radar, lidar, infotainment systems, cameras and vehicle-to-vehicle communications systems.  

To meet this need, the automotive industry—working with technology suppliers—has developed specialized communications protocols and application-specific extensions to existing network technologies, standardized under the aegis of organizations like ISO and IEEE, and it continues to investigate new topologies and protocols to improve performance, increase reliability and lower the costs of IVNs. Two recent developments have filled a longstanding gap in IVN architectures: CAN XL (up-to-20 Mbit/S extended length CAN) and 10Base-T1S (10 Mbit/S single-pair Ethernet), both of which operate in the 10 Mbit/S network space. What problems do these protocols solve and what opportunities do they present for IVN design?

Testing the DDR Memory Interface's Physical Layer (Part III)

Figure 1: For analysis purposes. it's critical to separate
read and write bursts of interest

Last time around, we began examining some of the challenges that come with testing the DDR interface's physical layer. In that post, we concentrated on getting to the devices' physical connections by various means including interposers, backside vias, and DIMM series resistors. Now, presuming we've managed to gain access to the DDR's ball-grid array, the next hurdle is separation of read and write bursts.

Testing the DDR Memory Interface's Physical Layer (Part I)

Figure 1: Clock, strobe, and data are
three critical signals in DDR test

In an earlier post, we took a brief tour through what constitutes a DDR memory interface: clock, command, address, and strobe+data lines linking a memory controller and an array of DRAM memory ICs. Next, we'll examine what DDR interface testing is all about, concentrating primarily on the physical layer.

Fundamentals of the DDR Memory Interface

Figure 1: A representative test setup
for physical-layer DDR testing

Double data-rate (DDR) memory has ruled the roost as the main system memory in PCs for a long time. Of late, it's seeing more usage in embedded systems as well. Let's look at the fundamentals of a DDR interface and then move into physical-layer testing (Figure 1).