Anatomy of a PCIe Link

Figure 1: A PCIe link between root complex and end point.
Each device has its own transmitter and receiver.

Peripheral Component Interconnect Express (PCIe®) is a high performance, general-purpose input/output (I/O) interconnect designed for a wide variety of computing and communication platforms. Recent iterations of the standard take advantage of high-speed serial technology, point-to-point interconnects, switch-based technology, and packetized protocol. They rely heavily on link negotiation and link training, so much so that being able to capture and view dynamic link behaviors is essential to debugging PCIe devices. Nevertheless, it remains a pain point for PCIe engineers. Why is it so difficult? To start, let’s break down the PCIe architecture to understand what is going on.

Some More PCIe 3.0 Test Examples (Part II)

Figure 1: This shows how a PeRT 3 state-machine log can be invaluable
in diagnosing timeouts in requests for presets

Continuing on from our last post, let's look at some more examples of common PCIe 3.0 test scenarios and how a well-equipped PCIe 3.0 testbench would approach them. Recall, if you will, that such a testbench would comprise a real-time digital oscilloscope of suitable bandwidth (such as Teledyne LeCroy's SDA830Zi-B oscilloscope), a protocol-enabled receiver tester (such as Teledyne LeCroy's PeRT 3 Phoenix System), and software that enables simultaneous, correlated views of the protocol and physical layers (such as Teledyne LeCroy's ProtoSync software).

Some PCIe 3.0 Test Examples (Part I)

Figure 1: Protocol and electrical views of
slow electrical response to a preset request

We took a tour of a typical PCIe 3.0 testbench setup in a recent post. Now, let's see that testbench in action with some application examples of some common bad behavior one might encounter from a PCIe 3.0 channel. These include: slow electrical response, slow protocol response, and so on.

An Under-The-Hood View of PCIe 3.0 Link Training (Part II)

Figure 1: A diagrammatic view of the
PCIe 3.0 dynamic link training process

Our last post in this series began examining the recovery.equalization process of PCIe 3.0 dynamic link training, beginning with Phases 0 and 1 of the process (Figure 1). Next, we will move on to take a closer look at Phases 2 and 3, where we'll see what can happen with devices in which the algorithms are not up to par. Namely, issues such as packet errors, dropped packets, and link retraining at lower data rates than 8 Gb/s.

PCIe 4.0 Transmitter Electrical Testing (Part I)

Figure 1: The two basic PCIe 4.0 transmitter tests
are shown above outlined in green

You've been introduced to some of the background and history that has brought the PCI Express protocol standard to its fourth generation, and we've discussed the test-equipment requirements for PCIe 4.0 electrical compliance testing. Let's begin examining the compliance testing, beginning with transmitter electrical tests.