Debugging Dynamic Link Behaviors with CrossSync PHY for PCIe

Figure 1: These upstream lanes show unexpected equalization
behavior. If you only had the electrical signals to work with,
how would you begin debugging them?

Recent generations of PCI Express® rely heavily on the link equalization process to support signal integrity at bit rates of 8, 16 or 32 Gbps. In Phase 1, both sides of the link exchange TS1 ordered sets to establish an operational link. In Phase 2, the upstream port requests the downstream port to configure its transmitter equalization to compensate for the link channel. In Phase 3, the opposite happens, and the downstream port requests the upstream port to configure its transmitter equalization. 

At PCI Express compliance events, or when doing pre-compliance testing in the lab, a transmitter link equalization test is performed to determine whether a device is capable of correct link equalization in isolation. A piece of test equipment, usually a protocol-aware BERT, acts as the link partner for the device under test. The BERT requests specific preset changes from the device, in response to which the device (in theory) changes its preset to provide the correct channel compensation. The changes are captured by an oscilloscope, which is capable of visualizing the transmitter equalization changes in the electrical layer and measuring first of all, if they happen quickly enough, and secondly, if the device actually changed to the preset levels requested, which occur in a known sequence. 

But what happens when you suspect "weird" equalization behavior in a live link between two devices—for example, something off with the upstream equalization in Phase 3?  How would you capture that to begin debugging the problem? Where would you look for a clue as to what is happening?

Feed-Forward Equalization

Figure 1: FFE creates a number of delayed versions of the
input signal that are then added back to the signal with
proper weights

In addition to continuous time linear equalization (CTLE), another means of improving signal quality at the receiver end of a high-speed serial data link is known as feed-forward equalization (FFE). In terms of implementation, FFE is not unlike the pre-emphasis filtering that is done on the transmitter side. An FFE implementation looks for all intents and purposes like a digital finite impulse response (FIR) filter.

The Effects of De-Emphasis on Eye Diagrams

Figure 1: This eye diagram of a serial-data stream as measured
at the receiver shows the effect a lossy channel has
on signal quality

Having discussed what transmit pre-emphasis is all about and the various ways in which it's implemented, it might be useful at this juncture to look at some examples of its application and the salutary effect it can have on the signal's eye diagram at the receiver end of the channel. Recall that there are two variations on pre-emphasis: de-emphasis and pre-shoot, which use different taps of a three-tap finite impulse response (FIR) filter to emphasize the last bit or the first bit of a bit sequence, respectively.

Introduction to Channel Equalization

Figure 1: Transmit pre-emphasis pre-distorts signals
in anticipation of the channel's effects

A number of factors can cause degradation of performance in a high-speed serial data link. Among them are inter-symbol interference (ISI) jitter, attenuation, reflections due to impedance mismatches, and insertion losses, to name a few. But fear not: There are techniques one may use to compensate for these losses known as equalization. We'll review the basics of channel equalization in today's post.