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Showing posts with label channel de-embedding. Show all posts
Showing posts with label channel de-embedding. Show all posts

19 October 2020

Which Virtual Probing Method to Use?

 

Virtual probing lets you "probe" where a probe can't reach, or compensate signals by deembedding or simulating devices and channels.
Virtual probing lets you "probe" where a probe
can't reach, or compensate signals by deembedding
or simulating devices and channels.
A great feature of Teledyne LeCroy oscilloscopes is the ability to apply virtual probing to compensate an input signal, whether by deembedding fixtures from the signal path, or simulating a “missing” component. It is especially helpful in cases where the signal is difficult to probe at the ideal location, hence the concept of “virtual” probing.

For example, because the JEDEC electrical specifications are defined at the balls of the DDR DRAM, it is often necessary to use the virtual probing capabilities of the oscilloscope to get the best representations of DDR signals to be analyzed with DDR Debug Toolkit or QualiPHY compliance software.

Here, we’ll give an overview of the virtual probing methods that become available with the installation of the SDAIII-CompleteLinQ or VirtualProbe software options, and some guidance as to which method is best to use in which case. And although we’ll show examples drawn from DDR analysis, the benefits of virtual probing are by no means limited to DDR signals.

10 July 2018

Serial-Data Channel Emulation and S Parameters

Higher data rates + "same old" channel media = degraded signal quality at receiver
Figure 1: Higher data rates + "same old" channel media
= degraded signal quality at receiver
Serial data rates have risen but propagation media for the channel remain unchanged, and that results in greater attenuation to the frequencies of interest. We could ignore these losses at lower frequencies, but now that rise times are so much faster, that's not an option. Channel effects now intrude into design margins to the point where eyes deteriorate and bit-error rates become unacceptable.

15 January 2018

PCIe 4.0 Receiver Link-Equalization Testing (Part II)

Working out the optimal combination of Tx emphasis presets and receiver CTLE settings
Figure 1: Working out the optimal combination of Tx emphasis
presets and receiver CTLE settings
As may be apparent from our previous post on PCIe 4.0 receiver link-equalization testing, this part of the PCIe 4.0 compliance tests is somewhat involved. When we left off last time, we were in the midst of receiver calibration, looking to ensure that the test-signal eye is as closed as possible without violating the specification limits.