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Showing posts with label PLL. Show all posts
Showing posts with label PLL. Show all posts

28 May 2015

The History of Jitter (Part V)

Applying PLLs for clock-data recovery is not unlike tapping your feet to the beat of music
Figure 1: Applying PLLs for clock-data recovery is not
unlike tapping your feet to the beat of music
A milestone in the history of jitter measurement came in the 1990s with receivers that could reveal the slowly varying component of jitter that became evident in time-interval error (TIE) tracks. That led to the advent of using phase-locked loops (PLLs) for clock-data recovery. In turn, PLLs opened new horizons in jitter analysis.

19 May 2015

The History of Jitter (Part IV)

An example of a time-interval error track
Figure 1: An example of a time-interval error track
In the previous installment in this series on the history of jitter, we'd reached the cusp of the new millennium. The in-vogue methodology for jitter analysis of the day was using edge crossing-point data in the form of a histogram and fitting Gaussian functions to the tails of the plot. But tail fitting, as we well know, isn't for the faint of heart. How would test methodologies move forward to surmount that hurdle?