You need to test, we're here to help.

You need to test, we're here to help.
Showing posts with label PCB. Show all posts
Showing posts with label PCB. Show all posts

30 August 2021

Debugging Complex Embedded Systems

Figure 1: A typical embedded system has many devices utilizing a wide range of signal types and bandwidths.
Figure 1: A typical embedded system has many devices
utilizing a wide range of signal types and bandwidths.
In the next few weeks, we’ll present a series of posts describing the debugging of various components of embedded systems, everything from working out the timing of power on sequences to extracting analog sensor data from serial data streams. All these examples of “real world” debugging can be performed using only standard tools available on most mid-range Teledyne LeCroy oscilloscopes.

Let's start by defining what we mean by embedded system and deeply embedded system. For our purposes, an embedded system is a fixed function, self-contained control system on one printed circuit board. Typically, printed circuit boards (PCBs)  will have multiple passive devices, a few active electronic devices, analog devices, digital devices and a few serial data devices. There tends to be a microcontroller device to process data and control other components. There will also be some type of system memory, often embedded inside the microcontroller. And, there will be some power conversion devices and power distribution elements that power all the other devices in your embedded system. 

23 April 2018

Investigating IoT Wireless Signals

Figure 1: Many IoT devices accept wireless antennas using U.FL connectors
Figure 1: Many IoT devices accept
wireless antennas using U.FL
connectors
Many IoT devices use wireless methods to communicate with other devices or with host systems. Just as with DC power-rail signals, probing of RF signals should be done with as little noise and as non-invasively as possible and with the best possible signal fidelity. Effective probing opens the door to Wi-Fi and Bluetooth signal analysis with RF demodulation, vector signal analysis, and spectrum analysis.

26 February 2018

Transmission Lines (Part III): Essential Principles

All interconnects are transmission lines with a signal path and a return path (not ground)
Figure 1: All interconnects are transmission lines with a signal
path and a return path (not ground)
Now that we've covered some of the principles and assumptions that underlie transmission lines in two prior posts, we can now directly address the topic with some essential principles that you need to understand.

22 January 2018

Setting the Stage for On-Die Power-Rail Measurements

Measuring on-die Vdd rail noise requires a suitably instrumented die and package
Figure 1: Measuring on-die Vdd rail noise requires
a suitably instrumented die and package
Armed with a suitable oscilloscope and active voltage-rail probe, you're now ready to make some power-rail measurements on a semiconductor die. Of course, making measurements on a die is a little different than making measurements on a printed-circuit board. This is where careful design-for-test at the die level comes in, because the chip, its packaging, and the board on which it will be mounted must be instrumented so as to make the on-die measurements possible.

15 November 2017

Probing Techniques and Tradeoffs (Part I)

Probes are the signal's gateway to the oscilloscope
Figure 1: Probes are the signal's gateway to the oscilloscope
As any oscilloscope user (hopefully) knows, probing is perhaps the most critical element of getting good measurement results (Figure 1). We must understand our probes' specifications to ensure that we obtain the best possible signal fidelity, and thereby accurately characterize our signal under test. In this series of posts, we'll take you through probing tradeoffs and techniques and help you choose the right probe for the task at hand.

11 April 2017

Testing the DDR Memory Interface's Physical Layer (Part II)

A typical BGA package for DDR memory
Figure 1: Shown is a typical BGA
package for DDR memory
In the first of this series of posts, we undertook a high-level view of physical test of a DDR memory interface. Moving forward, let's look into some of the specific challenges one faces in a close examination of these interfaces.