You need to test, we're here to help.

You need to test, we're here to help.
Showing posts with label BGA. Show all posts
Showing posts with label BGA. Show all posts

15 May 2018

Debugging DDR Memory on IoT Devices

Embedded systems such as IoT devices often require chip interposers to gain access to signal lines on DDR memory
Figure 1: Embedded systems such as IoT devices often require
chip interposers to gain access to signal lines on DDR memory
Internet of Things (IoT) devices are, at heart, just another embedded computing system, albeit one with an extremely well-defined function. As such, there's bound to be some amount of on-board data storage, and the storage medium of choice these days is typically double data-rate (DDR) memory. DDR memory transfers serial data on both the rising and falling edges of the clock signal, which is the characteristic from which it derives its name.

22 January 2018

Setting the Stage for On-Die Power-Rail Measurements

Measuring on-die Vdd rail noise requires a suitably instrumented die and package
Figure 1: Measuring on-die Vdd rail noise requires
a suitably instrumented die and package
Armed with a suitable oscilloscope and active voltage-rail probe, you're now ready to make some power-rail measurements on a semiconductor die. Of course, making measurements on a die is a little different than making measurements on a printed-circuit board. This is where careful design-for-test at the die level comes in, because the chip, its packaging, and the board on which it will be mounted must be instrumented so as to make the on-die measurements possible.

01 October 2014

DDR Memory Testing Part II: Using Interposers

The anatomy of a chip interposer
Figure 1: The anatomy of a chip interposer
If you're a PCB layout designer, you've probably heard one or more test engineers complain: "Why can't you lay out the board so that it can be tested?" All too often, components that need to be accessible to oscilloscope probes are physically inaccessible, whether it's because of close proximity of adjacent components or ball grid array (BGA) mounting of the DUT. It's nearly always a necessary evil, though, because of PCB cost and/or mechanical constraints.