Decision Feedback Equalization in DDR

Figure 1. A transmitted rectangular pulse suffers
distortion by the time it reaches the receiver. 
Broadening and reflections from previous
transmitted bits add to the pulse response, 
creating inter-symbol interference.

High-speed serial links such as those used in DDR4 and DDR5 are subject to a variety of signal degradation challenges.  Insertion losses, frequency dependent attenuation and inter-symbol interference (ISI), as well as others, are among the most commonly encountered sources of signal degradation. 

Figure 1 shows how reflections can cause ISI on a rectangular pulse. When a rectangular pulse is transmitted, it suffers distortion which is apparent when it reaches the receiver.  It may be broadened due to group delay dispersion because different frequency components of the signal propagate along the signal path at differing velocities. In addition, there may be echo pulses, due to impedance mismatches in the channel.  These mismatches cause reflections that propagate back and forth over the channel and appear as these echoes where subsequent bits should be.

Removing Reflections from DDR Signals Probed Mid-Bus

Figure 1. Virtual probing methods like VP@Rcvr can help
remove reflections from signals probed mid-bus.

Probing DDR signals can present some interesting challenges. The JEDEC specification indicates that all measurements should be made at the output pins of the memory chip. The challenge comes because sometimes the pins of the memory chip are not accessible. You may be able to use an interposer, but even that requires some spatial displacement from the probing point to the Ball Grid Array (BGA) pins of the memory chip. 

If the board has already been populated, there is an even greater problem because the interposer can’t be used, so probes may have to be placed in the middle of the bus in order to make a measurement. In this situation, the probe picks up signals reflected from the memory controller and the memory chip, as well as the desired signals. Reflections appear as non-monotonic ripples on the edges of DQ and DQS signals, as shown in Figure 2.

Isolating DDR Read and Write Operations

Figure 1. DDR DQ and DQS signals are
in phase during a Read operation and
out of phase during a Write operation.

Whether you are debugging or running compliance tests on Double Data Rate (DDR) or Low Power Double Data Rate (LPDDR) memory, the analysis process requires the separation of Read and Write operations to enable measurements on each distinct operational mode. 

The phase relationship between the Data (DQ) signal and the Data Strobe (DQS) signal indicates the type of operation, as shown in Figure 1.

The DQ and DQS signals are phase aligned with edges overlapping in Read mode. In Write mode, they are out of phase, and the DQS edge overlaps the center of the DQ eye.  In the lower speed versions of DDR memory devices, the measuring instrument could be triggered on this phase difference, enabling the isolation of the desired operation for testing.

Debugging DDR Memory on IoT Devices

Figure 1: Embedded systems such as IoT devices often require
chip interposers to gain access to signal lines on DDR memory

Internet of Things (IoT) devices are, at heart, just another embedded computing system, albeit one with an extremely well-defined function. As such, there's bound to be some amount of on-board data storage, and the storage medium of choice these days is typically double data-rate (DDR) memory. DDR memory transfers serial data on both the rising and falling edges of the clock signal, which is the characteristic from which it derives its name.

DDR Memory Testing Part IV: Preparing for Testing

Figure 1: For compliance testing,
DDR transition density should
be as high as possible

The first three installments of this series of posts on DDR memory testing are largely concerned with mechanical issues related to probing, use of interposers, and/or damping resistors. Now, we will turn our attention to the preliminaries of DDR testing itself: generating DDR traffic with which to exercise the memory interface, and criteria for a proper read/write burst pattern that will gain good test results.

DDR Memory Testing Part III: What Not to Do

Figure 1: Damping resistors on
solder-in probe tips

Testing of dual data-rate memory (DDR) devices and/or modules calls for careful application of some best practices for probing. There will also be cases where the use of chip interposers is called for. Heeding the advice provided in earlier Test Happens posts on this topic will go a long way toward successful probing and testing.

DDR Memory Testing Part II: Using Interposers

Figure 1: The anatomy of a chip interposer

If you're a PCB layout designer, you've probably heard one or more test engineers complain: "Why can't you lay out the board so that it can be tested?" All too often, components that need to be accessible to oscilloscope probes are physically inaccessible, whether it's because of close proximity of adjacent components or ball grid array (BGA) mounting of the DUT. It's nearly always a necessary evil, though, because of PCB cost and/or mechanical constraints.