DDR Memory Testing Part IV: Preparing for Testing

Figure 1: For compliance testing,
DDR transition density should
be as high as possible

The first three installments of this series of posts on DDR memory testing are largely concerned with mechanical issues related to probing, use of interposers, and/or damping resistors. Now, we will turn our attention to the preliminaries of DDR testing itself: generating DDR traffic with which to exercise the memory interface, and criteria for a proper read/write burst pattern that will gain good test results.

When setting up read/write burst traffic for exercising a DDR interface, the goal is to generate a high level of DDR transition density. A suitable memory diagnostic utility such as MemTest86 will do the trick; a recommended output from MemTest86 is Test 7, which continuously outputs read/write bursts for the duration of the test. For compliance testing, a burst should occur at least once every 10 μs, but in reality a much higher density is recommended. The higher the burst density, the more statistical results can be computed during a DDR compliance test (Figure 1).

DDR transition density is an important waveform characteristic for memory testing, but there are other important characteristics to check. The following is a signal checklist of characteristics to verify:

Figure 2: DDR signals should
exhibit given characteristics;
check these for correctness

• Check that CK (system clock), DQS (data strobe), DQ (data), and address/control signals are on the expected channels
• Verify that signal amplitudes are correct
• Validate that the CK signal is clean and at the proper frequency
• Verify the presence of read and write bursts
• Observe the relative amplitude of read and write bursts
• Validate proper idle signal levels

Further, the various signal lines should, in general, exhibit certain characteristics (Figure 2):

• Clock signal should be a continuous waveform
• DQS should appear as a bursted clock
• Data is also bursted but with somewhat less activity than DQS
• Address/control lines toggle slowly (either high or low)

Figure 3: Non-monotonic edges will wreak havoc
with DDR measurement timing

Don't overlook the need to maximize the dynamic range of your signal acquisition. For best results, signal amplitudes should occupy between 80% and 90% of the grid vertical area. Channel variable gain can be adjusted from your diagnostic software's compliance test menu.

Verification of the system clock entails ensuring that the frequency is as expected (2 × frequency = transfer rate). Additionally, the CK signal should not have any non-monotonic edges, which can create significant DDR measurement timing problems.

Regarding relative amplitudes, you can take some visual cues from the differences between read and write bursts. Read bursts should be in sync with DQS, while write bursts should be one-quarter out of sync with DQS. If probing is being done at the memory device, read bursts will have a larger amplitude and write bursts will have a smaller amplitude.

Lastly, check the idle levels on the signals. Look at portions of the waveforms where no data is being transmitted and measure the idle levels against these "rules of thumb": DQS should be 0 mV and DQ should be roughly 750 mV. In the case of a DDR3 line that's not being driven, the line will not stabilize at the logic-zero level (unlike NRZ signals, which always do). Rather, it stabilizes at a tri-state level somewhere between logic zero and logic one.

Hopefully, this gives you some idea of what to look for in preparing for DDR memory testing.