Choosing a High-voltage Oscilloscope Probe for SiC/GaN Power Semiconductor Device Measurements

Figure 1: Wide-bandgap (GaN) power semiconductor device
waveforms captured using two, different probe topologies.
Click on any image to expand.

In our last post, we introduced you to a new tool on the Teledyne LeCroy website: The High-voltage Probe Selection Guide. To demonstrate the benefits of the guide, let’s explore further what must be considered when choosing an HV oscilloscope probe for power semiconductor device measurements.

Why are power semiconductor device measurements challenging?

How to Choose the Best High-voltage Oscilloscope Probe in 5 Minutes

Figure 1: The High-voltage Probe Selection Guide
color codes better or worse probe selections based on
your answers to three, simple questions.
Click any image to enlarge.

Probing high-voltage (HV) circuits for analysis with an oscilloscope presents unique challenges due to the potential for injury or equipment damage, as well as the demands of the materials used in HV semiconductors. HV floating measurements are extremely dangerous and difficult to make. Conventional passive probes are not the answer, but isolated and high-voltage differential probes are options. Yet, with many possible choices in these categories, how can you decide which is actually the best HV oscilloscope probe for your application?

Teledyne LeCroy offers this new, easy way to help you select a high-voltage oscilloscope probe based on your specific application—the High-voltage Probe Selection Guide—available on the Teledyne LeCroy website at: teledynelecroy.com/powerprobes

Probing Techniques and Tradeoffs (Part IX): Best Practices

Figure 1: The typical manner
of using a hands-free probe
holder can cause issues

Having covered many of the theoretical aspects of probing signals, it's now useful to cover some best practices for high-speed active probing. We'll use some examples involving probing of DDR memory to illustrate what works best and what might not be a good idea from a practical standpoint.

DDR Memory Testing Part IV: Preparing for Testing

Figure 1: For compliance testing,
DDR transition density should
be as high as possible

The first three installments of this series of posts on DDR memory testing are largely concerned with mechanical issues related to probing, use of interposers, and/or damping resistors. Now, we will turn our attention to the preliminaries of DDR testing itself: generating DDR traffic with which to exercise the memory interface, and criteria for a proper read/write burst pattern that will gain good test results.

Eliminate Pitfalls of DDR Memory Testing

Figure 1: DDR test configuration
for a desktop computer

Since its inception as a standard in the mid 1990s, dual data-rate (DDR) SDRAM memory has been near ubiquitous in computing applications. Compared to single data-rate SDRAM, the DDR SDRAM interface makes higher transfer rates possible by more strict control of the timing of the electrical data and clock signals.