DDR Memory Testing Part IV: Preparing for Testing

Figure 1: For compliance testing,
DDR transition density should
be as high as possible

The first three installments of this series of posts on DDR memory testing are largely concerned with mechanical issues related to probing, use of interposers, and/or damping resistors. Now, we will turn our attention to the preliminaries of DDR testing itself: generating DDR traffic with which to exercise the memory interface, and criteria for a proper read/write burst pattern that will gain good test results.

DDR Memory Testing Part III: What Not to Do

Figure 1: Damping resistors on
solder-in probe tips

Testing of dual data-rate memory (DDR) devices and/or modules calls for careful application of some best practices for probing. There will also be cases where the use of chip interposers is called for. Heeding the advice provided in earlier Test Happens posts on this topic will go a long way toward successful probing and testing.

DDR Memory Testing Part II: Using Interposers

Figure 1: The anatomy of a chip interposer

If you're a PCB layout designer, you've probably heard one or more test engineers complain: "Why can't you lay out the board so that it can be tested?" All too often, components that need to be accessible to oscilloscope probes are physically inaccessible, whether it's because of close proximity of adjacent components or ball grid array (BGA) mounting of the DUT. It's nearly always a necessary evil, though, because of PCB cost and/or mechanical constraints.

Eliminate Pitfalls of DDR Memory Testing

Figure 1: DDR test configuration
for a desktop computer

Since its inception as a standard in the mid 1990s, dual data-rate (DDR) SDRAM memory has been near ubiquitous in computing applications. Compared to single data-rate SDRAM, the DDR SDRAM interface makes higher transfer rates possible by more strict control of the timing of the electrical data and clock signals.