Decision Feedback Equalization in DDR

Figure 1. A transmitted rectangular pulse suffers
distortion by the time it reaches the receiver. 
Broadening and reflections from previous
transmitted bits add to the pulse response, 
creating inter-symbol interference.

High-speed serial links such as those used in DDR4 and DDR5 are subject to a variety of signal degradation challenges.  Insertion losses, frequency dependent attenuation and inter-symbol interference (ISI), as well as others, are among the most commonly encountered sources of signal degradation. 

Figure 1 shows how reflections can cause ISI on a rectangular pulse. When a rectangular pulse is transmitted, it suffers distortion which is apparent when it reaches the receiver.  It may be broadened due to group delay dispersion because different frequency components of the signal propagate along the signal path at differing velocities. In addition, there may be echo pulses, due to impedance mismatches in the channel.  These mismatches cause reflections that propagate back and forth over the channel and appear as these echoes where subsequent bits should be.

Removing Reflections from DDR Signals Probed Mid-Bus

Figure 1. Virtual probing methods like VP@Rcvr can help
remove reflections from signals probed mid-bus.

Probing DDR signals can present some interesting challenges. The JEDEC specification indicates that all measurements should be made at the output pins of the memory chip. The challenge comes because sometimes the pins of the memory chip are not accessible. You may be able to use an interposer, but even that requires some spatial displacement from the probing point to the Ball Grid Array (BGA) pins of the memory chip. 

If the board has already been populated, there is an even greater problem because the interposer can’t be used, so probes may have to be placed in the middle of the bus in order to make a measurement. In this situation, the probe picks up signals reflected from the memory controller and the memory chip, as well as the desired signals. Reflections appear as non-monotonic ripples on the edges of DQ and DQS signals, as shown in Figure 2.

Isolating DDR Read and Write Operations

Figure 1. DDR DQ and DQS signals are
in phase during a Read operation and
out of phase during a Write operation.

Whether you are debugging or running compliance tests on Double Data Rate (DDR) or Low Power Double Data Rate (LPDDR) memory, the analysis process requires the separation of Read and Write operations to enable measurements on each distinct operational mode. 

The phase relationship between the Data (DQ) signal and the Data Strobe (DQS) signal indicates the type of operation, as shown in Figure 1.

The DQ and DQS signals are phase aligned with edges overlapping in Read mode. In Write mode, they are out of phase, and the DQS edge overlaps the center of the DQ eye.  In the lower speed versions of DDR memory devices, the measuring instrument could be triggered on this phase difference, enabling the isolation of the desired operation for testing.

Which Virtual Probing Method to Use?

 

Virtual probing lets you "probe" where a probe
can't reach, or compensate signals by deembedding
or simulating devices and channels.

A great feature of Teledyne LeCroy oscilloscopes is the ability to apply virtual probing to compensate an input signal, whether by deembedding fixtures from the signal path, or simulating a “missing” component. It is especially helpful in cases where the signal is difficult to probe at the ideal location, hence the concept of “virtual” probing.

For example, because the JEDEC electrical specifications are defined at the balls of the DDR DRAM, it is often necessary to use the virtual probing capabilities of the oscilloscope to get the best representations of DDR signals to be analyzed with DDR Debug Toolkit or QualiPHY compliance software.

Here, we’ll give an overview of the virtual probing methods that become available with the installation of the SDAIII-CompleteLinQ or VirtualProbe software options, and some guidance as to which method is best to use in which case. And although we’ll show examples drawn from DDR analysis, the benefits of virtual probing are by no means limited to DDR signals.

Examples of IoT DDR Debug Scenarios

Figure 1: Using the oscilloscope's Track
math function can help pin down
timing anomalies

Our last post considered some broad aspects of debugging DDR memory on Internet of Things (IoT) devices, such as how chip interposers can help with probing access and the benefits of virtual probing software. Let's now take a look at some particular examples of problems with these memory chips and their controllers and see how debugging with an oscilloscope might be approached.