Debugging Dynamic Link Behaviors with CrossSync PHY for PCIe

Figure 1: These upstream lanes show unexpected equalization
behavior. If you only had the electrical signals to work with,
how would you begin debugging them?

Recent generations of PCI Express® rely heavily on the link equalization process to support signal integrity at bit rates of 8, 16 or 32 Gbps. In Phase 1, both sides of the link exchange TS1 ordered sets to establish an operational link. In Phase 2, the upstream port requests the downstream port to configure its transmitter equalization to compensate for the link channel. In Phase 3, the opposite happens, and the downstream port requests the upstream port to configure its transmitter equalization. 

At PCI Express compliance events, or when doing pre-compliance testing in the lab, a transmitter link equalization test is performed to determine whether a device is capable of correct link equalization in isolation. A piece of test equipment, usually a protocol-aware BERT, acts as the link partner for the device under test. The BERT requests specific preset changes from the device, in response to which the device (in theory) changes its preset to provide the correct channel compensation. The changes are captured by an oscilloscope, which is capable of visualizing the transmitter equalization changes in the electrical layer and measuring first of all, if they happen quickly enough, and secondly, if the device actually changed to the preset levels requested, which occur in a known sequence. 

But what happens when you suspect "weird" equalization behavior in a live link between two devices—for example, something off with the upstream equalization in Phase 3?  How would you capture that to begin debugging the problem? Where would you look for a clue as to what is happening?

How Much Transmission-Line Loss is Too Much?

Figure 1: This plot represents the differential insertion-loss
profile for a 20" FR-4 microstrip trace

One of the fundamental facts of transmission lines is losses. Any effort to debug the performance of a high-speed serial data link begins there. But it begs an equally fundamental question: How much loss in a transmission line is too much? How do we quantify losses, and what is the connection between attenuation at the Nyquist frequency and the eye diagram? Is there a rule of thumb one might apply, some sort of rough estimate of how much loss might be too much for your channel to bear at a given data rate?

PCIe 4.0 Receiver Link-Equalization Testing (Part I)

Figure 1: PCIe 4.0 receiver link-equalization testing
takes place at the site of the channel's worst-case signal

In the battery of PCIe 4.0 compliance tests, there is but a single test of receiver behavior: Rx link-equalization testing. Given that our DUT in this test is an add-in card, we want to have our worst-case signal at the Card ElectroMechanical (CEM) connector (Figure 1). The signal then proceeds through the channel on the add-in card to the end point, which is the receiver on the DUT.

Gearing Up for PCIe 4.0 Electrical Compliance Test

Figure 1: A key element in PCIe 4.0
compliance test is a high-bandwidth,
real-time oscilloscope (shown is the
Teledyne LeCroy LabMaster 10Zi-A)

Armed with some of the background information and history on PCIe 4.0 electrical compliance testing, we're now ready to look at just what it takes in terms of test equipment to determine compliance for a PCIe 4.0 device. With the increase in data-transfer rate from 8 Gb/s in PCIe 3.0 to 16 Gb/s in PCIe 4.0, so too have the test equipment requirements advanced.