Introduction to Debugging High-Speed Serial Links

Figure 1: These images depict the degradation of serial data
traffic as it makes its way from transmitter to receiver

In recent years, the data rates in serial links have increased exponentially across any number of standard protocols, including PCI Express, USB, and even SATA and SAS. With higher data rates comes more challenges for system designers, validation engineers, and test engineers with respect to signal integrity (SI). Some SI effects are much more prominent at higher data rates than they were for lower-speed versions of the same protocols. In this series of posts, we'll examine these SI effects, look at some methods of improving system performance, and discuss some SI analysis solutions as well as measurement considerations.

PCIe 4.0 PLL Bandwidth Testing

Figure 1: PLL bandwidth testing
ensures that the add-in card's
PLL bandwidth and peaking
are within specifications

The final piece of the PCIe 4.0 compliance-test puzzle—at least until PCI-SIG completes its test definitions—is the PLL bandwidth test. This test, which is performed only on add-in cards, verifies that the PLL bandwidth and peaking are within the limits allowed by the PCIe 4.0 specification (Figure 1).

The Components of Total Jitter

Figure 1: An overview of the jitter hierarchy,
or "jitter tree," showing the various elements
that make up total jitter

In an earlier post, we began looking at the topic of jitter, a topic of keen interest to anyone working with high-speed serial communications or the components of such a system, including transmitters, receivers, and data channels. To gain an understanding of jitter, an important first step is getting to know a little about the various categories that comprise total jitter.