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| Figure 1: PCIe 4.0 receiver link-equalization testing takes place at the site of the channel's worst-case signal |
You need to test, we're here to help.
You need to test, we're here to help.
15 January 2018
PCIe 4.0 Receiver Link-Equalization Testing (Part I)
PCIe 4.0 Transmitter Link-Equalization Testing
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| Figure 1: Shown is an overview of the PCIe 4.0 link-equalization response test |
12 January 2018
PCIe 4.0 Transmitter Electrical Testing (Part II)
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| Figure 1: With an add-in card as our DUT, we will measure the transmit signal at the root complex on the system board |
PCIe 4.0 Transmitter Electrical Testing (Part I)
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| Figure 1: The two basic PCIe 4.0 transmitter tests are shown above outlined in green |
11 January 2018
Gearing Up for PCIe 4.0 Electrical Compliance Test
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| Figure 1: A key element in PCIe 4.0 compliance test is a high-bandwidth, real-time oscilloscope (shown is the Teledyne LeCroy LabMaster 10Zi-A) |
Introduction to PCIe 4.0 Electrical Compliance Test
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| Figure 1: PCI Express is now in its fourth generation and poses daunting physical-layer test challenges |
04 January 2018
Probing Techniques and Tradeoffs (Part VI): Dynamic Range
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| Figure 1: Differential-mode dynamic range is the maximum allowable voltage between the probe amplifier's inputs |
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