Testing the DDR Memory Interface's Physical Layer (Part II)

Figure 1: Shown is a typical BGA
package for DDR memory

In the first of this series of posts, we undertook a high-level view of physical test of a DDR memory interface. Moving forward, let's look into some of the specific challenges one faces in a close examination of these interfaces.

The first test challenge is simply accessing the signals of interest. These days, DRAM chips come in ball-grid-array (BGA) packages that are wave-soldered to a matching array of pads on the PCB (Figure 1). How does one get to those pads?

Figure 2: Interposers that sit between
the DRAM chip and PCB can
alleviate difficult signal access

Three common approaches to making BGA solder joints accessible include: backside vias, interposers, and DIMM series resistors. If they're included in the PCB layout, backside vias can be the ideal spot at which to probe DDR signals. Typically, good signal fidelity results from the vias' proximity to the termination. However, many devices, such as dual-rank DIMMs and dense embedded systems render this access option untenable.

Figure 3: DIMM series resistors are
a good alternative for dual-rank DIMMs

The second option of interposers can also be useful in difficult access situations (Figure 2). As with backside vias, interposers afford reasonably good signal fidelity. However, they impose additional complexity if the socket is to be installed correctly. In addition, the interposer's footprint can be problematic on crowded PCBs.

If dual-rank (or two-sided) DIMMs are involved, the backside vias won't be accessible. This makes DIMM series resistors a good alternate location for signal access (Figure 3). The downside of this approach is that the distance between the probe and the DRAM's terminations can result in problematic reflections from the receiver.

The next post in this series will look into another DDR test challenge: burst separation.