Testing the DDR Memory Interface's Physical Layer (Part III)

Figure 1: For analysis purposes. it's critical to separate
read and write bursts of interest

Last time around, we began examining some of the challenges that come with testing the DDR interface's physical layer. In that post, we concentrated on getting to the devices' physical connections by various means including interposers, backside vias, and DIMM series resistors. Now, presuming we've managed to gain access to the DDR's ball-grid array, the next hurdle is separation of read and write bursts.

The problem, simply stated, is this: read and write bursts share a bus, yet must be analyzed separately. Read bursts originate from the DRAM while write bursts originate from the controller. The bus is "tri-state" (high impedance at both ends) when neither side is transmitting (Figure 1). With all that said, it's critical to be able to identify and isolate read and write bursts of interest for analysis purposes.

Figure 2: Anatomy of a DDR read burst

Figure 2 illustrates the anatomy of a read burst. The DQ and DQS signals, begin in tri-state mode. The controller initiates a read command on the command bus. There is some amount of read latency between the time the command is issued and the burst is generated. At the burst's initiation, there is a preamble during which DQS comes out of idle in a prescribed manner prior to DQ transition. Following the burst, DQ and DQS return to their idle state. During the burst period, DQ and DQS are in phase with each other.

Figure 3: Phase-based burst separation
has its benefits and drawbacks

Like a read burst, write bursts begin with DQ and DQS in tri-state idle mode. And as with a read burst, the action kicks off with a write command from the controller. In fact, everything is the same with this exception: During the burst period, DQ and DQS are out of phase with each other (this is not the case for LPDDR4).

So what are your options for burst separation? The first, and most obvious, is to use the phase difference between the data (DQ) and strobe (DQS) lines to differentiate reads and writes. The advantage here is that identification is simple and requires only the signals being tested. On the downside, signals with lots of noise, reflections, or slow rise/fall times can make phase measurements, and hence burst separation, an unreliable approach (Figure 3).

A second option is to acquire and trigger on the command bus. This removes any possible uncertainty about the coming burst type. Here, the benefits are not only highly reliable separation, but also insight into the command-bus activity and its relationship to DQ/DQS. The disadvantage is the requirement to probe additional signals.

With burst separation achieved, the next step is to prepare for physical-layer test. We'll cover that preparation in the next post in this series.