Signal and Power Integrity Tutorial: Power Rail Probing for Rail Compression

Figure 3. Equivalent circuit of a typical CMOS I/O
showing the connection from the on-die rails
and the board-level test points.

By Prof. Eric Bogatin,
Teledyne LeCroy Fellow

Excerpted by permission from the Signal Integrity Journal article, Measuring Only Board-level Power Rail Noise May Be Misleading

Continued from Part 1.

Measuring Rail Compression on the Die

In most applications, we do not have access to the bare die when the chip is assembled on the circuit board. If the IC package has not been instrumented with special pass-through features connecting the rails on the die to board pins, we have to rely on a special trick. [The use of a quiet HIGH and quiet LOW]

When the I/Os of a chip all share the same power and ground rails, which is often the case in small microcontroller devices, designated I/Os can be used as sense lines to measure externally the power rails on the die.

Signal and Power Integrity Tutorial: How PDN Design Affects Board-level Noise

Figure 1. Oscilloscope traces resulting from 
measuring a 3.3. V power rail with a 10x probe
versus a coaxial connection, with an
adjacent 10x probe acting as an RF antenna.

By Prof. Eric Bogatin,
Teledyne LeCroy Fellow

Excerpted by permission from the Signal Integrity Journal article, Measuring Only Board-level Power Rail Noise May Be Misleading

In our blog, we’ve presented a lot about the impact of the interconnect on oscilloscope measurements, and how where you probe can be as important as how you probe. This article is an excellent demonstration of those very principles.

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Power rail measurements are important because they can identify potential sources of noise before they become a problem. However, measuring only the power rail noise at the board-level may be a misleading indication of the noise the die actually sees. 

Best Practices for Power Integrity Measurements

Measuring a power rail on a board seems like a simple task. Like all measurements, it is easy to get a waveform on the oscilloscope’s screen, but it is difficult to have confidence you have eliminated the measurement artifacts and have a realistic measure of the actual signal present.

Measuring Shared On-Die Power Rails

Figure 1: This schematic represents the signal paths
in typical, general-purpose I/Os

If you're taking power-rail measurements on a semiconductor die that is appropriately instrumented with sense lines and a direct connection to the die's core PDN, you're in pretty good shape. But what if that's not the case? If the die's I/O power rails are shared by the core power rails, here's a way to get your core power-rail measurements anyway.

A Walk-Through of Ground-Bounce Measurements

Figure 1: The trigger pulse from the
MCU is one clock cycle in width

In earlier posts in this series, we've explained what ground bounce is and how it happens. We have also taken a deeper dive into the use of I/O drivers to implement sense lines that let us better quantify and analyze what kind of ground-bounce hit our system is taking. Now, let's look at a detailed example of how to measure and diagnose ground bounce.