You need to test, we're here to help.

You need to test, we're here to help.

14 November 2014

An Under-the-Hood View of PCIe 3.0 Link Training

An overview of the elements of PCIe 3.0 dynamic link equalization
Figure 1: An overview of the elements of PCIe 3.0
dynamic link equalization
Now that we've looked at the basics of PCIe 3.0 dynamic link equalization and at some of the particulars of de-emphasis and preshoot, it's time to dive a little deeper into what actually happens in the link training process. It all happens in the blink of an eye but there's enough going on to warrant some dissection.

10 November 2014

PCIe 3.0 Dynamic Link EQ: De-Emphasis, Preshoot, Cursors, and Presets

De-emphasis, a key transmit-side equalization technique for PCIe 3.0, boosts high-frequency content
Figure 1: De-emphasis, a key transmit-side equalization
technique for PCIe 3.0, boosts high-frequency content
In an earlier post, we looked at some of the basics of dynamic link equalization for PCIe 3.0, and in particular the reasons why it's not only necessary but mandated by the PCI-SIG for compliance testing. Essentially, the boost in data rates from 5 GT/s in PCIe 2.0 to 8 GT/s in PCIe 3.0 wreaked havoc in terms of signal integrity in the channel. The solution is found in equalization both before (RxEQ) and after (TxEQ) the channel.

06 November 2014

The Hows and Whys of PCIe 3.0 Dynamic Link Equalization

SI problems are the root cause for dynamic link equalization in PCIe 3.0
Figure 1: SI problems are the root cause for
dynamic link equalization in PCIe 3.0
If you're designing a computer peripheral these days, chances are that you'll use the Peripheral Component Interconnect Express (PCIe) protocol for communication between the device and the host system. With the emergence of PCIe, a bunch of older bus standards were kicked to the curb. PCIe itself became the basis for more specialized standards, most notably ExpressCard for laptop expansion cards and SATA Express for storage interfaces.

15 October 2014

DDR Memory Testing Part IV: Preparing for Testing

For compliance testing, DDR transition density should be as high as possible
Figure 1: For compliance testing,
DDR transition density should
be as high as possible
The first three installments of this series of posts on DDR memory testing are largely concerned with mechanical issues related to probing, use of interposers, and/or damping resistors. Now, we will turn our attention to the preliminaries of DDR testing itself: generating DDR traffic with which to exercise the memory interface, and criteria for a proper read/write burst pattern that will gain good test results.

08 October 2014

DDR Memory Testing Part III: What Not to Do

Damping resistors on solder-in probe tips  terminating at chip interposer
Figure 1: Damping resistors on
solder-in probe tips
Testing of dual data-rate memory (DDR) devices and/or modules calls for careful application of some best practices for probing. There will also be cases where the use of chip interposers is called for. Heeding the advice provided in earlier Test Happens posts on this topic will go a long way toward successful probing and testing.

01 October 2014

DDR Memory Testing Part II: Using Interposers

The anatomy of a chip interposer
Figure 1: The anatomy of a chip interposer
If you're a PCB layout designer, you've probably heard one or more test engineers complain: "Why can't you lay out the board so that it can be tested?" All too often, components that need to be accessible to oscilloscope probes are physically inaccessible, whether it's because of close proximity of adjacent components or ball grid array (BGA) mounting of the DUT. It's nearly always a necessary evil, though, because of PCB cost and/or mechanical constraints.

24 September 2014

Eliminate Pitfalls of DDR Memory Testing


DDR test configuration for a desktop computer
Figure 1: DDR test configuration
for a desktop computer
Since its inception as a standard in the mid 1990s, dual data-rate (DDR) SDRAM memory has been near ubiquitous in computing applications. Compared to single data-rate SDRAM, the DDR SDRAM interface makes higher transfer rates possible by more strict control of the timing of the electrical data and clock signals.