You need to test, we're here to help.

You need to test, we're here to help.

15 October 2014

DDR Memory Testing Part IV: Preparing for Testing

For compliance testing, DDR transition density should be as high as possible
Figure 1: For compliance testing,
DDR transition density should
be as high as possible
The first three installments of this series of posts on DDR memory testing are largely concerned with mechanical issues related to probing, use of interposers, and/or damping resistors. Now, we will turn our attention to the preliminaries of DDR testing itself: generating DDR traffic with which to exercise the memory interface, and criteria for a proper read/write burst pattern that will gain good test results.

08 October 2014

DDR Memory Testing Part III: What Not to Do

Damping resistors on solder-in probe tips  terminating at chip interposer
Figure 1: Damping resistors on
solder-in probe tips
Testing of dual data-rate memory (DDR) devices and/or modules calls for careful application of some best practices for probing. There will also be cases where the use of chip interposers is called for. Heeding the advice provided in earlier Test Happens posts on this topic will go a long way toward successful probing and testing.

01 October 2014

DDR Memory Testing Part II: Using Interposers

The anatomy of a chip interposer
Figure 1: The anatomy of a chip interposer
If you're a PCB layout designer, you've probably heard one or more test engineers complain: "Why can't you lay out the board so that it can be tested?" All too often, components that need to be accessible to oscilloscope probes are physically inaccessible, whether it's because of close proximity of adjacent components or ball grid array (BGA) mounting of the DUT. It's nearly always a necessary evil, though, because of PCB cost and/or mechanical constraints.

24 September 2014

Eliminate Pitfalls of DDR Memory Testing


DDR test configuration for a desktop computer
Figure 1: DDR test configuration
for a desktop computer
Since its inception as a standard in the mid 1990s, dual data-rate (DDR) SDRAM memory has been near ubiquitous in computing applications. Compared to single data-rate SDRAM, the DDR SDRAM interface makes higher transfer rates possible by more strict control of the timing of the electrical data and clock signals.

05 September 2014

Back to Basics: Using The Display Graticule

The oscilloscope display graticule
Figure 1: The display graticule, the grid of intersecting lines
overlaying the signal display area, is the original
oscilloscope measurement tool
Today's digital oscilloscopes come packed with an abundance of measurement capabilities, all available at the touch of a button or two. Want to know the amplitude of a square wave? Easy. Want to know the standard deviation of that amplitude? Minimum/maximum or mean? All easily compiled for you over hundreds or thousands of acquisitions.

20 August 2014

Go Back to School on Signal Integrity

No matter how much we might think we know about signal integrity, there's always more to learn. The laws of physics never change but we might come across new scenarios in which to apply them. Circuits with higher levels of functionality are constantly being squeezed into smaller, more portable spaces; the closer together we pack active components and transmission lines, the more acute their sensitivity is to electromagnetic energy. Everything's either a transmitter or a receiver in some sense and everything has effects on other components, intended or otherwise.

05 August 2014

Back to Basics: History Mode

Initial setup of WaveSurfer 3000 oscilloscope
Figure 1: Initial setup of WaveSurfer 3000 with a
2-MHz pulse waveform fed into Channel 1
Back in the day, one of the biggest deficiencies of early digital oscilloscopes was their lack of memory depth. A memory of 500 or 1000 points was about as good as it got, and this didn't provide much in the way of detailed waveform capture. Today's instruments are very different animals; for example, Teledyne LeCroy's recently introduced WaveSurfer 3000 oscilloscopes offer up to 10 Mpoints of memory per channel.