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You need to test, we're here to help.

17 December 2014

What S-parameters Reveal About Interconnects (Part III)

How ripple is introduced into S11 and S21
Figure 1: How ripple is introduced into S11 and S21
S-parameters are a great tool for understanding exactly what happens to a signal as it traverses an interconnect such as a transmission line. How much of it propagates through, and how much reflects off of impedance mismatches? From plotting return loss against insertion loss, we've weighed how much return loss may be tolerable before it significantly impacts insertion loss. Now we'll turn our attention to some common patterns exhibited by S11 and S21 and what they mean to the performance of an interconnect.

09 December 2014

What S-parameters Reveal About Interconnects (Part II)

Measuring S-parameters of a two-port interconnect
Figure 1: Measuring S-parameters
of a two-port interconnect
Having previously covered some of the fundamentals of S-parameters, it's now time to dig a little deeper into what they can show us about an interconnect; say, for example, a two-port microstrip line on a PC board. Unlike the one-port DUT in our earlier post, this configuration gives us the opportunity to look at not only S11 (return loss or reflected signal), but also S21 (insertion loss or transmitted signal).

03 December 2014

What S-Parameters Reveal About Interconnects

S-parameters are derived by applying an incident wave to an interconnect
Figure 1: S-parameters are derived by applying an incident
wave to an interconnect; we can consider this process in either
the time or frequency domains
S-parameters are a popular means of characterizing an interconnect. By feeding the interconnect with a precision reference signal and measuring how much of that signal propagates through the connector and how much is reflected, we learn everything we need to know about its performance. This will be the first in a series of posts about the insights we can glean from S-parameters with practical examples of common measurement scenarios.

14 November 2014

An Under-the-Hood View of PCIe 3.0 Link Training

An overview of the elements of PCIe 3.0 dynamic link equalization
Figure 1: An overview of the elements of PCIe 3.0
dynamic link equalization
Now that we've looked at the basics of PCIe 3.0 dynamic link equalization and at some of the particulars of de-emphasis and preshoot, it's time to dive a little deeper into what actually happens in the link training process. It all happens in the blink of an eye but there's enough going on to warrant some dissection.

10 November 2014

PCIe 3.0 Dynamic Link EQ: De-Emphasis, Preshoot, Cursors, and Presets

De-emphasis, a key transmit-side equalization technique for PCIe 3.0, boosts high-frequency content
Figure 1: De-emphasis, a key transmit-side equalization
technique for PCIe 3.0, boosts high-frequency content
In an earlier post, we looked at some of the basics of dynamic link equalization for PCIe 3.0, and in particular the reasons why it's not only necessary but mandated by the PCI-SIG for compliance testing. Essentially, the boost in data rates from 5 GT/s in PCIe 2.0 to 8 GT/s in PCIe 3.0 wreaked havoc in terms of signal integrity in the channel. The solution is found in equalization both before (TxEQ) and after (RxEQ) the channel.

06 November 2014

The Hows and Whys of PCIe 3.0 Dynamic Link Equalization

SI problems are the root cause for dynamic link equalization in PCIe 3.0
Figure 1: SI problems are the root cause for
dynamic link equalization in PCIe 3.0
If you're designing a computer peripheral these days, chances are that you'll use the Peripheral Component Interconnect Express (PCIe) protocol for communication between the device and the host system. With the emergence of PCIe, a bunch of older bus standards were kicked to the curb. PCIe itself became the basis for more specialized standards, most notably ExpressCard for laptop expansion cards and SATA Express for storage interfaces.

15 October 2014

DDR Memory Testing Part IV: Preparing for Testing

For compliance testing, DDR transition density should be as high as possible
Figure 1: For compliance testing,
DDR transition density should
be as high as possible
The first three installments of this series of posts on DDR memory testing are largely concerned with mechanical issues related to probing, use of interposers, and/or damping resistors. Now, we will turn our attention to the preliminaries of DDR testing itself: generating DDR traffic with which to exercise the memory interface, and criteria for a proper read/write burst pattern that will gain good test results.