You need to test, we're here to help.

You need to test, we're here to help.

27 February 2015

Using Histograms (Part II)

Figure 1: A flip-flop's propagation delay is a typical spec that can be derived using statistical analysis
Figure 1: A flip-flop's propagation delay is a typical spec
that can be derived using statistical analysis
In Part I of this series, we looked at some of the basics of histograms and how they can provide a statistical view into random variation of signal parameters. Next, let's look at how histograms can help us use statistical analysis to determine product specifications.

09 February 2015

Using Histograms (Part I)

Histograms of the period, width, and TIE of a clock waveform show different distributions of  time jitter
Figure 1: Histograms of the period, width,
and TIE of a clock waveform show
different distributions of time jitter
When we measure parameters of a waveform in a circuit or device, we rarely take a single measurement but rather a significant number of measurements. We want to see trends over time in the period, width, and time-interval error of a clock pulse, for example. Those parameters will have some nominal value, but there will typically be some random variation that we refer to as jitter.

30 January 2015

Plan For Successful USB Compliance Testing (Part III)

In USB 3.0 link-layer compliance test, all logical states of the LTSSM come into play
Figure 1: In USB 3.0 link-layer compliance test,
all logical states of the LTSSM come into play
In Part I and Part II of this series on USB compliance test, we've looked at some of the basic information on compliance testing and at some aspects of physical-layer test, respectively. In this third part of the series, we'll turn our attention to USB 3.0 link-layer testing.

26 January 2015

Plan For Successful USB Compliance Testing (Part II)

A representative transmitter compliance test setup
Figure 1: A representative transmitter
compliance test setup
In the first post in this series, we looked at some of the basics of USB 3.0 and 3.1 compliance test and covered the USB-IF's role in overseeing the protocol. Now, let's look into some aspects of physical-layer test.

16 January 2015

Plan For Successful USB Compliance Testing (Part I)

The coveted USB 3.1 logo
Figure 1: The coveted SuperSpeed USB logo
Certifying a device's implementation of a serial protocol standard is a fairly complex process involving a number of levels: electrical test, interoperability, backward compatibility, link layer, and so on. Generally, some organization oversees a given protocol, managing the revision process for the protocol itself as well as the testing process that a product must undergo. Passing the relevant compliance test suite and having a valid Trademark License Agreement on file bestows the prized right to display the protocol's logo on the product's box (Figure 1). That logo's presence tells the product's users that their device's serial interface operates within parameters set by the overseeing organization.

30 December 2014

Filtering Signals with MATLAB

A 2-pole, 1-MHz Butterworth low-pass filter applied to an acquired waveform
Figure 1: A 2-pole, 1-MHz Butterworth low-pass filter
applied to an acquired waveform
Touted by its maker as "the language of technical computing," The MathWorks' MATLAB is a veritable Swiss Army knife for engineers, scientists, and perhaps anyone involved in technical endeavors. MATLAB serves a myriad of applications in programming, data analysis, application development, modeling and simulation, and... wait for it... instrument control!

17 December 2014

What S-parameters Reveal About Interconnects (Part III)

How ripple is introduced into S11 and S21
Figure 1: How ripple is introduced into S11 and S21
S-parameters are a great tool for understanding exactly what happens to a signal as it traverses an interconnect such as a transmission line. How much of it propagates through, and how much reflects off of impedance mismatches? From plotting return loss against insertion loss, we've weighed how much return loss may be tolerable before it significantly impacts insertion loss. Now we'll turn our attention to some common patterns exhibited by S11 and S21 and what they mean to the performance of an interconnect.