## You need to test, we're here to help.

You need to test, we're here to help.

## 29 August 2018

### A Walk-Through of Ground-Bounce Measurements

 Figure 1: The trigger pulse from the MCU is one clock cycle in width
In earlier posts in this series, we've explained what ground bounce is and how it happens. We have also taken a deeper dive into the use of I/O drivers to implement sense lines that let us better quantify and analyze what kind of ground-bounce hit our system is taking. Now, let's look at a detailed example of how to measure and diagnose ground bounce.

For demonstration purposes, we've instrumented an Arduino MCU (some details on how that was done are here) as our DUT. The test equipment we used is a Teledyne LeCroy WavePro HD oscilloscope and RP4030 active power-rail probe (there's lots more detail on the RP4030 in our series of posts on power-rail measurements, especially this one). The combination will reveal a great deal of detail on our DUT's susceptibility to ground bounce while sidestepping the common challenges of measuring power rails.

 Figure 2: The measured Vss noise on the quiet-low line with one I/O switching is low
Our MCU will generate a trigger pulse that starts a series of a three-output pulse pattern: the first with no I/Os switching, a second with one I/O switching, and a third with two I/Os switching. Let's look at our trigger pulse first. In Figure 1, Channel 1 on our oscilloscope is looking at the trigger signal. The code controlling the MCU was written so that the trigger pulse's width is one clock cycle. The MCU runs off a 16-MHz clock, so the clock period, 1/(16 MHz), is about 60 ns. With the timebase set at 100 ns/div, the pulse width looks about right. Measuring it shows a width of 63 ns. The 10%-90% rise time of our trigger pulse is 3.2 ns. Fall time is about 6 ns.

Next, we'll turn on Channel 2 of our oscilloscope, which is acquiring the quiet-low line with one I/O switching. We're using Ch1 as our trigger on the rising edge. Figure 2 shows us our trigger pulse on Ch1 and our ground bounce on the quiet-low line on Ch2 (overlaid in magenta). As we can see, there's not a lot of ground bounce happening, mostly because there's not very much of a load on the I/O. All it's done is to charge up a bit of cable capacitance. If there were a lower resistive load (lower impedance), there would be more switching current and more ground bounce on Ch2.

 Figure 3: Ground bounce is much more pronounced when two I/O drivers are switching at one time
At the third trigger pulse, both I/Os switch, and that produces a bit more ground bounce. The Δi/Δt generates voltage noise on the ground rail (Figure 3). When switching is from low to high, we're getting a negative voltage on the ground rail. The positive pulse on the high-to-low transition and negative pulse on the low-to-high transition are both ground bounce pulses on the ground rail.

Note, however, the noise on the quiet-low line before the trigger pulse even occurs. This is because Vss on the die is shared by the I/Os and the core logic. Even when there's no triggering taking place, the MCU sits "idle" but it's really doing lots of things, such as running a watchdog timer, doing self-testing, and other logic operations. Each of those means PDN current flows through the Vss pin, into the ground plane of the board, and ultimately to the regulator.

The same measurement technique can be applied to a quiet-high line to examine the Vdd rail. Were one to apply another RP4030 active power-rail probe, you would see that when Vss is bouncing up, Vdd/Vcc would be pulling down. Both rails go into a sort of collapse that is known as power-rail compression. The voltage difference between Vdd and Vss decreases when we have PDN activity flowing from high to low.

It is recommended to use an active probe for these measurements so that the probe isn't loading down the rail. Ideally, the probe should offer high bandwidth, high impedance at low frequencies, and be able to handle a high offset for looking at small voltages.

In an upcoming post, we'll start looking at more of the fundamental issues that cause ground bounce. We'll discuss the sorts of interconnect structures where it's likely to happen, and some best design practices for keeping it at bay.

Previous posts in this series:
About Ground Bounce and How to Measure It
More on Quiet-Low I/O Drivers and Ground Bounce