|Figure 1: For analysis purposes. it's critical to separate|
read and write bursts of interest
The problem, simply stated, is this: read and write bursts share a bus, yet must be analyzed separately. Read bursts originate from the DRAM while write bursts originate from the controller. The bus is "tri-state" (high impedance at both ends) when neither side is transmitting (Figure 1). With all that said, it's critical to be able to identify and isolate read and write bursts of interest for analysis purposes.
|Figure 2: Anatomy of a DDR read burst|
|Figure 3: Phase-based burst separation|
has its benefits and drawbacks
So what are your options for burst separation? The first, and most obvious, is to use the phase difference between the data (DQ) and strobe (DQS) lines to differentiate reads and writes. The advantage here is that identification is simple and requires only the signals being tested. On the downside, signals with lots of noise, reflections, or slow rise/fall times can make phase measurements, and hence burst separation, an unreliable approach (Figure 3).
A second option is to acquire and trigger on the command bus. This removes any possible uncertainty about the coming burst type. Here, the benefits are not only highly reliable separation, but also insight into the command-bus activity and its relationship to DQ/DQS. The disadvantage is the requirement to probe additional signals.
With burst separation achieved, the next step is to prepare for physical-layer test. We'll cover that preparation in the next post in this series.