|Figure 1: Applying PLLs for clock-data recovery is not|
unlike tapping your feet to the beat of music
Using PLLs for clock-data recovery was key to analysis of bit streams such as USB, in which there is only data and no clock. The idea was to find the bit rate sans clock and track it in a fashion analogous to how we tap our feet to music to track the beat.
|Figure 2: On the left is a full TIE histogram,|
while on the right is a TIE histogram
from which data-dependent jitter
has been stripped away
|Figure 3: Using FFT to find peaks|
in a random jitter TIE track
|Figure 4: With peaks removed, integrate|
the noise floor to find the sigma
of the Gaussian distribution
With the dawn of the 2000s, signal integrity issues came to the forefront. The problem had shifted: How do we transmit NRZ data with growing bit rates through FR4 PCB material, which was never designed for such applications? Starting at an easy 2.5-Gb/s rate, there is very little signal attenuation at a fundamental frequency of 1.25 GHz. But by the time the bit rate gets to 5 Gb/s or higher, attenuation is significant.
|Figure 5: A 5-Gb/s bit stream before|
an FR4 channel (left) and after the
same channel (right)
The answer to this problem, of course, was equalization, which we began using to compensate for increased jitter due to frequency-dependent losses and ISI. We'll examine how equalization comes into the picture in the next installment of our history of jitter.