Plan For Successful USB Compliance Testing (Part III)

Figure 1: In USB 3.0 link-layer compliance test,
all logical states of the LTSSM come into play

In Part I and Part II of this series on USB compliance test, we've looked at some of the basic information on compliance testing and at some aspects of physical-layer test, respectively. In this third part of the series, we'll turn our attention to USB 3.0 link-layer testing.

First, why is it important to test the USB 3.0 link layer? The link layer is fundamental to the interface's functionality. Problems at the link layer make the benefits of USB SuperSpeed traffic impossible. Functionally speaking, the link layer:

• facilitates reliable delivery of header packets
• enables receiver detection.
• controls link training and bring-up
• manages entry and exit from low-power states
• signals and detects in-band reset
• performs link error handling.

Without reliable delivery of header packets, the link performance drops off, battery management suffers, and, perhaps most importantly, logo certification is out of the question.

Compliance test for the USB 3.0 link layer is a substantial undertaking. First, the device must pass USB 2.0 link layer compliance test, and then undergo the incremental USB 3.0 testing. Among the items tested are link and packet robustness, CRC error handling, invalid link commands, timer deadlines, LGOOD/LCRD sequences, U0-U3 under controlled conditions, and link reset. The link training status state machine (LTSSM) shown in Figure 1 represents all of the logical states that a SuperSpeed USB link may enter during normal operation. There are specific rules for entry and exit of each and every one of these logical states, and all of them must pass compliance testing.

Figure 2: The USB 3.0 link-polling substates

The link polling substates are where link initialization happens (Figure 2). With RX detect, the transmitter determines that there is in fact a receiver terminating the far end of the channel. Then both devices move to a polling state, which includes several substates. After an initial low-frequency periodic signaling (LFPS) handshake, receiver equalization (RX_EQ) commences.

In the RX_EQ substate, the receiver is to achieve the 5 Gb/s signal lock. To do so, both transmitter and receiver send a predefined sequence of 65,536 training sequence equalization (TSEQ) symbols. Here, the receiver is supposed to calibrate the transmitter. If both sides acknowledge receipt, they move on to the Polling Active (TS1) state, in which the two sides are to receive eight TS1 symbols followed by 16 Polling Configuration (TS2) symbols. If the receiver does not see eight TS1 symbols, the devices cycle between RX detect and Polling Active. Additionally, several configuration fields are extracted from the TS2 sequence. After detection of Logical Idle, the link exits the polling states and the link moves to the U0 state.

If the ports under test fail to complete link training, this is where it would occur. All of the above is covered in the TD.7.01 link bring-up test. We'll look more closely at details of the testing in a future post.