Rise-Time Degradation and ISI Jitter

Figure 1: Shown are the signals from two extreme bit patterns
overlaid on top of each other with no interconnect in the channel

In discussing inter-symbol interference (ISI), the phenomenon in which information "leaks" from one bit to subsequent bits, we've identified a couple of root causes of ISI jitter. The first is reflection losses caused by impedance discontinuities, while the second is group delay dispersion, a consequence of the differing propagation speeds of different frequencies through a given material. We looked at these forms of distortion in both the time and frequency domains.

A third root cause of ISI jitter is rise-time degradation, which in turn is an artifact of frequency-dependent losses. Let's consider two extreme bit patterns, both transmitted at the same bit rate with a rise time of about 50 ps:

• 11111010000000, and
• 00000010000000

Figure 2: The addition of a 20-inch interconnect
introduces some ISI jitter

Figure 1 shows the two patterns overlaid atop one another. In this instance, there are no interconnects in the channel. Obviously, the pattern beginning with the string of ones is in red; the pattern beginning with the string of zeroes is in blue. Note that the transition points for both patterns exactly coincide. 

If we introduce a 20-inch interconnect but keep everything else the same, we can see that the interconnect affects the two bit patterns in different ways (Figure 2). The red trace exhibits the effects of the "echoes of a bit past," or the leakage of one bit into subsequent bits, in the increased voltage level that results in a transition time that's different from what it should be. ISI is now causing horizontal jitter. Because the rise time has degraded and the signal's slew rate is much lower than it was at the transmitter, these effects become more pronounced. 

Figure 3: Going from a 20-inch interconnect to a 40-inch
interconnect creates an enormous amount of ISI jitter

The effects become worse still with the introduction of a 40-inch interconnect (Figure 3). The difference in the transmission times is very large. Each bit pattern will be affected differently as they traverse the same channel at the same data rate. This is why ISI is sometimes referred to as "data-dependent" jitter. It is channel-dependent as much as it is pattern-dependent.

But at the end of the day, the switching threshold time for the "1" bit is different when the previous bits were all zeroes from when they were all ones. The more rise-time degradation there is, the more deterministic jitter results.

Figure 4: A lossy channel means bad eye diagrams, high jitter,
and ultimately high bit-error rates in your serial link

To summarize, we've been looking at the effects of distortion of a serial-data signal going through a lossy channel from transmitter to receiver. Referring to Figure 4, what leaves the transmitter (eye diagram at top left) ends up at the receiver looking pretty sad (eye diagram at top right). The losses in the channel due to the lossiness of typical PCB FR-4 attenuates the signal and severely degrades the eye diagram, resulting in poor eye margins, high jitter, and ultimately high bit-error rates.

All is not lost, though. Next, we'll turn our attention to some of the equalization techniques you can use on both the transmitter side and the receiver side to rescue your serial-data link's performance.

Previous posts in this series:

Introduction to Debugging High-Speed Serial Links
A Look at Transmission-Line Losses
How Much Transmission-Line Loss is Too Much?
Inter-Symbol Interference (or Leaky Bits)