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23 August 2021

Measuring Dead Time in 48 V Power Conversion Systems, Part I: Static Measurements

48 volt power conversion systems input a 48 VDC power bus and output other voltage levels. The key section in the conversion process is the inverter stage. The inverter subsection topology may be half bridge, full or H-bridge, or cascaded H-bridge for 3-phase systems. There is typically a filtering circuit after the inverter before power is passed on to the Load, and a control system that takes care of controlling the entire conversion system. 

Figure 1:Three common topologies for switching inverter stages. The load is connected between upper and lower power switching devices, which are selectively switched on and off to supply power to the load from the DC bus.

The three inverter topologies shown in Figure 1 are all similar in that they use stacked or “totem pole” power devices for switching. 

In operation, each of these topologies provides a path from the DC bus through the load and then to ground (0 V) by turning on selected devices. At no time should there be a direct path from the DC bus to ground, an event called “shoot through.” Designers intentionally add dead time to eliminate the risk of shoot through.

Dead time is time added to the gate driver of the power FETs to ensure the avoidance of shoot through caused by both gates being simultaneously open to load. The dead time is measured as the delay from LO1 turning off and HI1 turning on, and vice versa. The measured delays must be positive, indicating both devices are not on at the same time.

Consider the operation of the simplest topology, the half bridge. Power switching devices are modelled by simple switches in Figure 2.

Figure 2: A simplified model of a half bridge inverter operation. HI and LO switches are closed alternately so that the load is either connected to the 48 V bus or to ground.

Dead time is measured for two different states—first as the time delay between the HI side switch being open and the LO side switch being closed, then as the time delay between the LO side switch being open and the HI side switch being closed. The dead time in either case must be greater than zero seconds. This assures that both switches are not closed simultaneously.

Equipment for Making Inverter Dead Time Measurements

The inverter topology determines the number of channels that are required in order to debug the circuit. At minimum, the input and output of each switching device should be measured in order to see the critical timing relationships. That means four channels for a half bridge inverter, eight channels for an H-bridge inverter, and twelve channels for a cascaded H-bridge inverter. 4- or 8-channel oscilloscopes are commonly available, beyond which there are options like OscilloSYNC™ that link oscilloscopes to increase the channel count.

Figure 3: Simplified functional diagram of a
48 V buck converter showing locations of the
eight probing points used to debug the circuit.
Consider setting up a measurement on a 48 V DC-DC buck converter using a half-bridge topology implemented with a GaN field effect transistor (FET), as shown in Figure 3. The numbers on the diagram indicate the locations being probed.

Using an 8-channel oscilloscope allows for measuring more than the four device-related signals. By also measuring the bus voltage, output voltage and output current, parametric effects due to source and load variations on VGS and VDS waveforms can be seen, making dynamic dead time measurements possible.

In these examples, HVD3000 Series High Voltage Differential Probes were used for test points 5 through 7.  These probes offer high CMRR over a broad frequency range with very low noise. The voltage (VGS) of both the High side and Low side FETs were measured using a DL-HCM High Common Mode Differential Probe, which is optimized for high bandwidth 48 V signals.

The probes are connected to the gate and source terminals of both the upper and lower GaN FETs and the signals on both devices are captured in oscilloscope C1 and C3 (Figure 4). The acquired HI and LO gate drive signals appear as traces C1 and C3 in the top left and second from top left grids.  Zoom traces Z1 and Z3 show a horizontally expanded view of the two traces in the left bottom grid. 

Figure 4: Acquired gate drive signals from the lower and upper GaN FETs.
The horizontally expanded zoom view of the raw acquisition shows some high frequency pickup.
Applying a 100 MHz low pass filter eliminates the pickup.

 The zoom traces show some high frequency ringing at about 350 MHz.  The ringing is due to pick up on the probe connections and can be filtered out by applying a 100 MHz low pass filter.  The filtered waveforms appear as traces F1 and F3 in the upper right grids.  Zooms of the filtered traces appear in the bottom right grid.  The filtering has greatly reduced the ringing amplitude.  Deadtime is measured on two sets of edges VGS Low turning off while VGS High turns on and VGS High turning off while VGS Low turns on.

Measuring Dead Time

Figure 5: Dead time is measured as the time delay between
VGS Low (LO1) turning off and VGS High (HI1) turning on
and the delay of VGS High turning off and VGS Low turning on.
At its most basic, this measurement can be made using the oscilloscope’s relative time cursors by setting the cursor indicators at the 50% amplitude points on both waveforms and measuring the time difference.

A more convenient and accurate measurement can be made using delta time at level (Dtime@level). Figures 6 and 7 show the setup for the delta time at level measurement. Two parameters must be specified: Dtime@level1 (Figure 6) marks the location of the VGS Low turning off. The slope is negative, and the threshold amplitude is 50%. Conversely, Dtime@level2 (Figure 7) sets the location of the VGS High turning on. The slope is positive, and the threshold amplitude is 50%.

Figure 6: Dtime@level1 specifies location of VGS Low off.

Figure 7: Dtime@level2 specifies location of VGS High on.

After setting up the parameters, check the Show Table box on the Measure dialog to display the measurement values (Figure 8).

Parameters are measured over all instances recorded in the acquired waveform. Figure 8 shows ten thousand Dtime@level measurements were made, but the Value displayed in the table is the value for the last of each of these measurements. 

Figure 8: The two Dtime@level parameters, P2 and P3, are displayed below the traces.

Using Pass/Fail Testing to Monitor Dead Time Measurements

It is possible to monitor dead time measurements using Pass/Fail testing of the parameters values. Pass/Fail testing can be found under the oscilloscope's Analysis pull down menu. Pass/Fail testing involves setting a Pass or Fail condition on the occurrence of a specified event, in this case the measurement falling short of a specific value that marks the desired minimum dead time limit. The composite Figure 9 shows the setup for Pass/Fail testing on the Dtime@level2 parameter.

Figure 9: Pass/Fail test setup monitoring for measurements that fall short of a minimum limit.

Pass/Fail condition Q2 compares the parameter P2 results to a minimum limit, and likewise condition Q3 compares parameter P3 results (the setup is the same as for Q2 shown). The parameter comparison test flags any P2 or P3 measurement that is less than or equal to 1.5 ns. An alternative to setting a fixed limit as done here is to select a range of values, either absolute or falling within a certain Sigma of the measurement statistical mean. Since the device only “Passes if” Q2 and Q3 are always false (All False)—meaning the dead time measured is never under 1.5 ns—whenever either becomes True, the device Fails.

On the event of a device Fail, the oscilloscope can save the waveform, stop the acquisition, emit a beep alarm, emit a pulse, save a LabNotebook, or (on some oscilloscopes) take another user-defined action.

Once Pass/Fail testing is set up, it will continuously monitor the parameter values until the prescribed Pass or Fail condition occurs, at which time it will take the selected action.

See more tips in the on-demand webinar, Best Practices for Debugging 48 V Power Conversion Systems.


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