You need to test, we're here to help.

You need to test, we're here to help.

13 September 2017

Automotive Ethernet Compliance: Tests in Detail (Part I)

Maximum transmitter output droop should not exceed the specified maximum of 45%
Figure 1: Maximum transmitter output droop should not
exceed the specified maximum of 45%
We've looked in past posts at the basics of Automotive Ethernet compliance test, the five test modes, and an overview of the test setup. Now it's time to begin examining the physical-layer electrical tests in detail. As we've mentioned, there are a total of seven of these tests (six for BroadR-Reach and 100Base-T1 and one for the latter only).

The first test is for maximum transmitter output droop and is performed using test mode #1. The test measures both positive and negative transmitter output droop and compares it to the test limit of 45%. If you pay regular attention to the BroadR-Reach specification, you'll note that the test limit for this parameter has varied over the years. It began at 45%, then was reduced to 26.9%, and then reset at 45%.

Locating the initial positive and negative transmit peaks and measuring Vdrooped 500 ns later
Figure 2: Locating the initial positive and negative transmit
peaks and measuring Vdrooped 500 ns later
The first step in this test is to find where the transmit waveform crosses zero and step along that waveform until we locate the initial peak (Vpk+ and Vpk-) in transmit output (Figure 2). Next, we move 500 ns forward in time and, at that point, measure both the positive and negative Vdrooped values. Incidentally, note that we'd stated in an earlier post that the symbol period for test mode #1 must be at least 500 ns in duration, or at least 34 symbols at 100 Mb/s. This is the reason for that requirement.

Once you have values for Vpk+ and Vpk-, calculate droop as = 100 x (Vdrooped/Vpk), and compare the result to the test limit of 45%.

In the second test, which is for transmitter clock frequency, we will verify that the frequency of the transmitted clock meets the specification. This test uses test mode #2, which comprises a sine wave transmitted from the device in master transmission mode. The test limit for symbol transmission rate is 66.66 Mbaud ±100 ppm.

Fortunately, the transmitter clock frequency test is a simple matter. If your oscilloscope is so equipped, simply turn on measurement of the frequency (or bit rate) parameter. If, for instance, you're measuring a nominal 33.3-MHz clock, you would create a pass/fail condition with an absolute delta (being a plus/minus range that accommodates the 100-ppm window). Note that 33 MHz is half the baud rate, because it takes two symbols to create one cycle.

In our next installment, we'll turn to the transmitter timing jitter (master and slave, respectively).


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gowrishankargupta said...

Thanks for this article.
Also, please let us know under what conditions, droop > 45%. what are the debug points to check why such an issue could have happened?

Teledyne LeCroy said...

gowrishankargupta, apologies for the great delay in replying.

The Test Mode 1 pattern leaves the transmitter as a square wave. The Transmitter Output Droop test is performed at the connector to verify that the signal arrives with not more than a 45% drop in amplitude (droop).

Between these two points, the signal goes through a Low-pass Filter (LPF) and Common Mode Choke (CMC). This filtering is often designed to alleviate EMI/EMC issues on the signal path.

The droop test is performed to ensure that there is not excessive filtering happening between the transmitter output and the MDI output (connector). If the droop is > 45%, the LPF and/or the CMC are excessively impacting the signal and need adjustment so that the effect is not as extreme.

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