An Inside Look at an Automotive Ethernet Seminar

Figure 1: Students gain first-hand experience in
Automotive Ethernet protocol testing

Teledyne LeCroy's Automotive Technology Center (ATC) in Farmington Hills, MI recently hosted a full-day seminar on Automotive Ethernet. Below, Bob Mart, product line manager, shares some of his thoughts on how the seminar went and provides a preview of Teledyne LeCroy's next live Automotive Ethernet day at the ATC on June 15, 2017 (detailed information on this and other automotive-related events can be found here).

Testing the DDR Memory Interface's Physical Layer (Part IV)

Figure 1: Probes are a key element of the total signal
acquisition system

In this multipart survey of testing the DDR interface's physical layer, we've looked at the basics of the interface itself, a high-level overview of the testing, how to access DDR signals, and read/write burst separation. In this installment, we'll cover preparation for the actual testing.

Testing the DDR Memory Interface's Physical Layer (Part III)

Figure 1: For analysis purposes. it's critical to separate
read and write bursts of interest

Last time around, we began examining some of the challenges that come with testing the DDR interface's physical layer. In that post, we concentrated on getting to the devices' physical connections by various means including interposers, backside vias, and DIMM series resistors. Now, presuming we've managed to gain access to the DDR's ball-grid array, the next hurdle is separation of read and write bursts.

Testing the DDR Memory Interface's Physical Layer (Part II)

Figure 1: Shown is a typical BGA
package for DDR memory

In the first of this series of posts, we undertook a high-level view of physical test of a DDR memory interface. Moving forward, let's look into some of the specific challenges one faces in a close examination of these interfaces.

Testing the DDR Memory Interface's Physical Layer (Part I)

Figure 1: Clock, strobe, and data are
three critical signals in DDR test

In an earlier post, we took a brief tour through what constitutes a DDR memory interface: clock, command, address, and strobe+data lines linking a memory controller and an array of DRAM memory ICs. Next, we'll examine what DDR interface testing is all about, concentrating primarily on the physical layer.

Fundamentals of the DDR Memory Interface

Figure 1: A representative test setup
for physical-layer DDR testing

Double data-rate (DDR) memory has ruled the roost as the main system memory in PCs for a long time. Of late, it's seeing more usage in embedded systems as well. Let's look at the fundamentals of a DDR interface and then move into physical-layer testing (Figure 1).

Back to Basics: Three-Phase Sinusoidal Voltages

Figure 1: Three-phase AC voltages
consist of three voltage vectors

In a previous post, we briefly covered the basics of single- and three-phase AC power systems. Single-phase systems, as we've noted, comprise a single voltage vector with a magnitude (in VAC) and a phase angle. Of course, a three-phase voltage consists of three voltage vectors and three phase angles. This installment will go on to describe three-phase AC voltages in similarly brief fashion.