You need to test, we're here to help.

You need to test, we're here to help.

14 December 2020

Removing Reflections from DDR Signals Probed Mid-Bus

Figure 1. Virtual probing methods like VP@Rcvr can help remove reflections from signals probed mid-bus.
Figure 1. Virtual probing methods like VP@Rcvr can help
remove reflections from signals probed mid-bus.
Probing DDR signals can present some interesting challenges. The JEDEC specification indicates that all measurements should be made at the output pins of the memory chip. The challenge comes because sometimes the pins of the memory chip are not accessible. You may be able to use an interposer, but even that requires some spatial displacement from the probing point to the Ball Grid Array (BGA) pins of the memory chip. 

If the board has already been populated, there is an even greater problem because the interposer can’t be used, so probes may have to be placed in the middle of the bus in order to make a measurement. In this situation, the probe picks up signals reflected from the memory controller and the memory chip, as well as the desired signals. Reflections appear as non-monotonic ripples on the edges of DQ and DQS signals, as shown in Figure 2.

07 December 2020

Isolating DDR Read and Write Operations

Figure 1. DDR DQ and DQS signals are in phase during a Read operation and out of phase during a Write operation.
Figure 1. DDR DQ and DQS signals are
in phase during a Read operation and
out of phase during a Write operation.
Whether you are debugging or running compliance tests on Double Data Rate (DDR) or Low Power Double Data Rate (LPDDR) memory, the analysis process requires the separation of Read and Write operations to enable measurements on each distinct operational mode. 

The phase relationship between the Data (DQ) signal and the Data Strobe (DQS) signal indicates the type of operation, as shown in Figure 1.

The DQ and DQS signals are phase aligned with edges overlapping in Read mode. In Write mode, they are out of phase, and the DQS edge overlaps the center of the DQ eye.  In the lower speed versions of DDR memory devices, the measuring instrument could be triggered on this phase difference, enabling the isolation of the desired operation for testing.

30 November 2020

Oscilloscope Basics: Multiplexed Front Panel Controls

Fig. 1. Modern, slim front panel.
Fig. 1. Modern,
slim front panel.
Most Teledyne LeCroy oscilloscopes are equipped with traditional front panel controls—knobs and buttons—that are a (literally) handy way to make basic acquisition settings such as gain, timebase and trigger level. While all these could be made using the oscilloscope software, using the front panel allows you to keep dialogs closed and more of the screen “real estate” available for viewing traces as you modify these settings.

In order to optimize that real estate, front panels have become increasingly slim, and many front panel controls on newer Teledyne  LeCroy oscilloscopes are multiplexed, meaning they have multiple functions or can be used to control multiple on-screen objects. Here is a list of tips to keep in mind when using the front panel.

09 November 2020

Fundamentals of Power Integrity: Mutual Aggressors and Rail Transient Response Measurement

Fig 1. Rail droop in response to a load step is a typical case of mutual aggressors in a PDN.
Fig 1. Rail droop in response to a load step is
a typical case of mutual aggressors in a PDN.
A third type of noise found in PDNs is what we call mutual aggressors, which is crosstalk coupling from one component of the PDN onto another.

An obvious example is a load step in the PDA, where something in the system being turned on pulls current from the VRM that supplies a rail. In Figure 1, you can see how the output voltage of the VRM supplying a 1 V rail droops in response to a load step before it recovers. This is still noise: it is a signal variation that we're not expecting and don't want.

We want to be able to characterize that noise, because too much droop could affect the operation of other components that are already consuming power from that device.

In order to do so, we’re going to measure the rail transient response to the load application. We need only look at two signals: the voltage and the current on the rail of interest. Figure 1 shows the voltage on C5 (the green trace) and the current on C8 (the orange trace).

02 November 2020

Your Ground Bounce Questions Answered

Figure 1. Line set to "quiet low" shows ground bounce occurring as I/O driver switches.
Figure 1. Line set to "quiet low" shows ground
bounce occurring as I/O driver switches.
During an October 2020 webinar, Don’t Let Ground Bounce RuinYour Day, Dr. Eric Bogatin was asked several questions regarding his topic of presentation. Here are his answers.

Q: From what frequency should we consider ground bounce to be a problem?

A: Ground bounce is really due to a dI/dt. Generally, it becomes a problem with rise times shorter than 100 ns. The bandwidth of this is about 3.5 MHz. This means ground bounce can be an issue at relatively low frequency.

19 October 2020

Which Virtual Probing Method to Use?

 

Virtual probing lets you "probe" where a probe can't reach, or compensate signals by deembedding or simulating devices and channels.
Virtual probing lets you "probe" where a probe
can't reach, or compensate signals by deembedding
or simulating devices and channels.
A great feature of Teledyne LeCroy oscilloscopes is the ability to apply virtual probing to compensate an input signal, whether by deembedding fixtures from the signal path, or simulating a “missing” component. It is especially helpful in cases where the signal is difficult to probe at the ideal location, hence the concept of “virtual” probing.

For example, because the JEDEC electrical specifications are defined at the balls of the DDR DRAM, it is often necessary to use the virtual probing capabilities of the oscilloscope to get the best representations of DDR signals to be analyzed with DDR Debug Toolkit or QualiPHY compliance software.

Here, we’ll give an overview of the virtual probing methods that become available with the installation of the SDAIII-CompleteLinQ or VirtualProbe software options, and some guidance as to which method is best to use in which case. And although we’ll show examples drawn from DDR analysis, the benefits of virtual probing are by no means limited to DDR signals.

21 September 2020

Fundamentals of Power Integrity: Board Pollution

Figure 1. "Pollution" occurring on PDN traces.
Figure 1. "Pollution" occurring on PDN traces.
Board pollution is noise occurring on the packages and interconnects (traces and planes) that carry current from the VRMs to the consumer devices.
One place it can originate is from the VRM itself, for example, with the switching noise the VRM generates (Figure 1). That can be a real concern if the board capacitance means you have a resonance around the switching frequency that would act as an amplifier for the switching noise and cause all kinds of problems with other devices on the board.