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Showing posts with label LPDDR. Show all posts
Showing posts with label LPDDR. Show all posts

17 January 2022

9 Quick Fixes to Improve DDR Probing

Figure 1: Reversed Handsfree mounts and chip clips help relieve strain on fragile solders.
Figure 1: Reversed Handsfree mounts and chip
clips help relieve strain on fragile solders.
Probing at DRAM pins as required by JEDEC can be challenging. Here are nine, simple ways to improve your DDR probing.

1. Use positioning tools to relieve strain on probe tips

The Handsfree probe holder included as an accessory with several Teledyne LeCroy probes, such as the WaveLink and DH Series probes, was originally designed to put weight on the probe tip to ensure a good contact. However, many DDR probing applications utilize solder-in (SI) tips, where the greater concern is to relieve strain on the tip so as to not disrupt the solder. It turns out that if you use the Handsfree in a “reverse mounted” orientation (Figure 1), it puts the amplifier in a perfect position to help relieve strain on probe tips.

04 January 2021

Decision Feedback Equalization in DDR

Figure 1. A transmitted rectangular pulse suffers distortion by the time it reaches the receiver.  Broadening and reflections from previous transmitted bits add to the pulse response,  creating inter-symbol interference.
Figure 1. A transmitted rectangular pulse suffers
distortion by the time it reaches the receiver. 
Broadening and reflections from previous
transmitted bits add to the pulse response, 
creating inter-symbol interference.

High-speed serial links such as those used in DDR4 and DDR5 are subject to a variety of signal degradation challenges.  Insertion losses, frequency dependent attenuation and inter-symbol interference (ISI), as well as others, are among the most commonly encountered sources of signal degradation. 

Figure 1 shows how reflections can cause ISI on a rectangular pulse. When a rectangular pulse is transmitted, it suffers distortion which is apparent when it reaches the receiver.  It may be broadened due to group delay dispersion because different frequency components of the signal propagate along the signal path at differing velocities. In addition, there may be echo pulses, due to impedance mismatches in the channel.  These mismatches cause reflections that propagate back and forth over the channel and appear as these echoes where subsequent bits should be.

14 December 2020

Removing Reflections from DDR Signals Probed Mid-Bus

Figure 1. Virtual probing methods like VP@Rcvr can help remove reflections from signals probed mid-bus.
Figure 1. Virtual probing methods like VP@Rcvr can help
remove reflections from signals probed mid-bus.
Probing DDR signals can present some interesting challenges. The JEDEC specification indicates that all measurements should be made at the output pins of the memory chip. The challenge comes because sometimes the pins of the memory chip are not accessible. You may be able to use an interposer, but even that requires some spatial displacement from the probing point to the Ball Grid Array (BGA) pins of the memory chip. 

If the board has already been populated, there is an even greater problem because the interposer can’t be used, so probes may have to be placed in the middle of the bus in order to make a measurement. In this situation, the probe picks up signals reflected from the memory controller and the memory chip, as well as the desired signals. Reflections appear as non-monotonic ripples on the edges of DQ and DQS signals, as shown in Figure 2.

07 December 2020

Isolating DDR Read and Write Operations

Figure 1. DDR DQ and DQS signals are in phase during a Read operation and out of phase during a Write operation.
Figure 1. DDR DQ and DQS signals are
in phase during a Read operation and
out of phase during a Write operation.
Whether you are debugging or running compliance tests on Double Data Rate (DDR) or Low Power Double Data Rate (LPDDR) memory, the analysis process requires the separation of Read and Write operations to enable measurements on each distinct operational mode. 

The phase relationship between the Data (DQ) signal and the Data Strobe (DQS) signal indicates the type of operation, as shown in Figure 1.

The DQ and DQS signals are phase aligned with edges overlapping in Read mode. In Write mode, they are out of phase, and the DQS edge overlaps the center of the DQ eye.  In the lower speed versions of DDR memory devices, the measuring instrument could be triggered on this phase difference, enabling the isolation of the desired operation for testing.