Isolating DDR Read and Write Operations

Figure 1. DDR DQ and DQS signals are
in phase during a Read operation and
out of phase during a Write operation.

Whether you are debugging or running compliance tests on Double Data Rate (DDR) or Low Power Double Data Rate (LPDDR) memory, the analysis process requires the separation of Read and Write operations to enable measurements on each distinct operational mode. 

The phase relationship between the Data (DQ) signal and the Data Strobe (DQS) signal indicates the type of operation, as shown in Figure 1.

The DQ and DQS signals are phase aligned with edges overlapping in Read mode. In Write mode, they are out of phase, and the DQS edge overlaps the center of the DQ eye.  In the lower speed versions of DDR memory devices, the measuring instrument could be triggered on this phase difference, enabling the isolation of the desired operation for testing.

It’s not as easy to accomplish this with the newer and higher speed DDR chips, like DDR4 and DDR5.  The shorter clock periods relative to the higher transfer speeds make the phase triggering technique less reliable.  Also, LPDDR interfaces tend to have a lot of reflections, which can confuse the measurements, as shown in Figure 2.

Figure 2. Signal reflections can cause a
Read to be misinterpreted as a Write.

This LPDDR measurement shows a Read event misidentified as a Write event due to the reflection shifting the phase to the center of the DQ Write eye, as can happen when the determination of the operating mode is based solely on the phase of the DQS signal relative to the DQ signal.

The most reliable way to separate the Read and Write operations is to acquire and use the digital signals of the DDR command bus. This requires the ability to access both analog and digital signals using a high-bandwidth oscilloscope.  The Teledyne LeCroy DDR test solution pairs a WaveMaster or LabMaster oscilloscope with our HDA125 High-speed Digital Analyzer and DH Series High-bandwidth Probes (Figure 3) for high-speed mixed-signal input. The HDA125 adds 9 or 18 channels of digital input sampled at 12.5 GS/s to our high-performance oscilloscopes. Its 3 GHz bandwidth leadset can capture digital signals clocked at up to 6 GB/s.

Figure 3. Teledyne LeCroy DDR test solution combines high-speed analog and digital input.

The HDA125 digital leads are connected to the DDR command bus signal’s Chip Select not (CS-n), Write Enable not (WE_n), Row Address Stobe not (RAS_n), Column Address Strobe not (CAS-n) and clock lines.

Figure 4. DDR Debug Toolkit Bus View is a synchronized
view of analog DQ and DQS, and digital command bus.

Both the analog signals and digital lines can then be displayed on the oscilloscope in a composite Bus View using the DDR Debug Toolkit software, as shown in Figure 4. The Bus View is a complete view of the DDR burst including data, strobe and command bus.  The DDR Debug Toolkit separates the Read and Write operations based on the command bus signals and clearly marks them with a colored overlay--red for the Write operation and blue for the Read operation. The overlays appear on both the analog signals and the command bus lines, showing the relationship between them. 

As the command bus is decoded, the contents are summarized in a table beneath the signal display grids that shows the timing, burst length and command activity for each burst. DDR triggering is based on the command bus state, rather than the analog signal phase difference.

Read/Write separation using the command bus acquired by the HDA125 is also supported in Teledyne LeCroy’s QualiPHY DDR compliance test packages, so the same precision tools and method that let you debug DDR memory can help you test compliance to the JEDEC specification.

To learn more about DDR testing and our DDR solutions, watch the on-demand webinar, DDR4/5 & LPDDR4/5 Probing and Debug Solutions.

Also see:

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