PCIe 4.0 PLL Bandwidth Testing

Figure 1: PLL bandwidth testing
ensures that the add-in card's
PLL bandwidth and peaking
are within specifications

The final piece of the PCIe 4.0 compliance-test puzzle—at least until PCI-SIG completes its test definitions—is the PLL bandwidth test. This test, which is performed only on add-in cards, verifies that the PLL bandwidth and peaking are within the limits allowed by the PCIe 4.0 specification (Figure 1).

Figure 2: Shown is the connection schematic
for the PCIe 4.0 PLL bandwidth test

The PLL bandwidth test is essentially a jitter transfer function measurement, intended to check that the -3dB point of the DUT's jitter transfer function is within an acceptable frequency range and that the jitter transfer function does not exhibit excessive peaking.

Figure 3: Plotting a curve of the
jitter transfer for each frequency

To perform this test, we'll use the test setup shown in Figure 2. the BERT's subrate clock output to intentionally apply calibrated jitter to the reference clock used by the DUT. We apply a defined amount of sinusoidal jitter, S_j, across the PLL-bandwidth measurement range to a 100-MHz subrate clock. Then we'll measure the periodic jitter, P_j, at the device transmitter at each frequency using the oscilloscope.

The results are obtained by simply plotting a curve of the jitter transfer for each frequency, and comparing the results to the specification limits (Figure 3).

This completes our overview of the PCIe 4.0 compliance tests, at least until there is more information to share regarding the tests still under definition, which include: transmitter pulse-width jitter, lane margining timing, and lane margining voltage (Figure 1, again). We'll provide a post updating this series at that time.



















Earlier posts in this series:

Introduction to PCIe 4.0 Electrical Compliance Test
Gearing Up for PCIe 4.0 Electrical Compliance Test
PCIe 4.0 Transmitter Electrical Testing (Part I)
PCIe 4.0 Transmitter Electrical Testing (Part II)
PCIe 4.0 Transmitter Link-Equalization Testing
PCIe 4.0 Receiver Link-Equalization Testing (Part I)
PCIe 4.0 Receiver Link-Equalization Testing (Part II)