PCI Express 4.0 Error Detection Using a BERT and Oscilloscope

Figure 1: BERT and Oscilloscope connection
for PCI Express 4.0 error detection.

The PCI Express® 4.0 standard specification requires an oscilloscope with at least 25 GHz analog bandwidth and a BERT which can test bit rates of at least 16 Gbps. The BERT provides a known input pattern to the PCIe® device under test (DUT), and the DUT is instructed to regenerate the identical bit pattern while placed in loopback mode. Since a BERT can output a signal when a bit error is detected, this signal can be input to the oscilloscope to trigger a synchronized capture when an error occurs. By combining the capabilities of these two instruments, a powerful combination of real-time error detection and characterization can emerge.

Connecting the Instruments

In Figure 1, a known pattern is connected from the BERT PPG D1 output to the PCIe DUT input via a 2.92 mm K-type cable. The DUT attempts to regenerate the same data pattern, while the DUT output is routed to both the BERT error detector input and the oscilloscope channel 1 via 2.92 mm K-type tables and a power splitter. An error-free reference signal is connected between the BERT D2 output to the oscilloscope channel 2, along with the error trigger signal from the error detector output to the oscilloscope channel 3. An oscilloscope Edge trigger is set on the rising edge of the error detector output signal on C3.

Error Detection Method

In order to determine the jitter tolerance of a PCIe device, controlled quantities of random and sinusoidal jitter are injected into the signal by the BERT. At some point, the DUT will likely fail to repeat the same pattern applied to its output, resulting in a bit error. 

Figure 2: Zoom of “error flag” trace
identifies the precise bit error location.

Shown in Figure 2, the oscilloscope triggers on the error detector output and captures all three waveforms. Using an oscilloscope Math function, the PCIe reference waveform with no errors (pink C2) is subtracted from the PCIe waveform with potentially errored bits (yellow C1) to create an “error flag” waveform (green F4). Since the green waveform is the difference between the potentially errored waveform (yellow) and the error-free reference waveform (pink), when the device is running error-free, the green waveform will ideally display a flat line indicating that no errors have occurred. However, when a bit error occurs, the difference between the two waveforms will produce an error flag, since one waveform is in a high state while the other is in a low state during that bit period. The error flag shown in Figure 2 is due to the yellow waveform showing a logic 1 while the reference waveform shows a logic 0 at the same time position. A zoom of the error flag (green Z4) visually indicates where the bit error occurs.

The error flag points to the precise location in time where the bit error has occurred, which can be quantified by measuring the time between the error detector trigger and the error flag edge (P2). With the error location in time precisely identified, and the oscilloscope's ability to capture other waveforms, the source of the error can be correlated with other signals for root cause-and-effect analysis. By combining the BERT's ability to stream data in actual time with the oscilloscope's ability to capture and display the waveform shape details when the event occurs, the exact error location can be identified and viewed, allowing for advanced debug capabilities far beyond what either instrument can provide independently.

Download this information in our application note on PCIe 4.0 Error Detection Using a BERT and Oscilloscope.