Test Happens.

Figure 1: An overview of the elements of PCIe 3.0 dynamic link equalization Now that we've looked at the basics of PCIe 3.0 dynamic...

Figure 1: De-emphasis, a key transmit-side equalization technique for PCIe 3.0, boosts high-frequency content In an earlier post , we l...

Figure 1: SI problems are the root cause for dynamic link equalization in PCIe 3.0 If you're designing a computer peripheral these ...

Figure 1: For compliance testing, DDR transition density should be as high as possible The first three installments of this series of ...

Figure 1: Damping resistors on solder-in probe tips Testing of dual data-rate memory (DDR) devices and/or modules calls for careful app...

Figure 1: The anatomy of a chip interposer If you're a PCB layout designer, you've probably heard one or more test engineers com...

Figure 1: DDR test configuration for a desktop computer Since its inception as a standard in the mid 1990s, dual data-rate (DDR) SDRAM...